VCVTTSD2SI

VCVTTSD2SI is the VEX and EVEX form of CVTTSD2SI: the low double of an XMM register or of eight bytes of memory, truncated toward zero to a signed 32-bit or 64-bit integer in a general-purpose register. CVTTSD2SI’s page covers the cases that matter for doubles, and VCVTTSS2SI what the encodings change: VEX.vvvv and EVEX.vvvv must be 1111b, the EVEX form (AVX-512F or AVX10.1) reaches XMM16 to XMM31 and takes {sae} but no rounding mode, and the VEX form needs AVX.

Recorded on Zen 5#

• Under MXCSR 3FC0h, rounding down, vcvttsd2si ecx, xmm12 truncated 2,147,483,647.5 to 7FFFFFFFh and set PE: the largest result the 32-bit form can give, from a double that a single could not hold.
• {evex} vcvttsd2si r14d, xmm5, {sae} gave 80000000h for 2^31, which does not fit, with the invalid exception unmasked (MXCSR 1E40h) and no #XM: MXCSR stayed as it was.
• With FTZ and DAZ set (FFC0h), the smallest normal double, 2^-1022, from memory gave 0 and set PE; DAZ turns only denormal inputs into zeros.
• A signaling NaN gave 8000000000000000h in the 64-bit form and set IE.

In compiled code#

In our builds at -O2 with -march=x86-64-v3, testing whether a double holds an integer, x == (int)x, separates the compilers. GCC 14 keeps the round trip: VCVTTSD2SI, then VXORPS and VCVTSI2SD back, then VUCOMISD. Clang 23 drops the conversion and truncates in a vector register with vroundsd xmm1, xmm0, xmm0, 0xb before a VCMPEQSD, which at -v4 writes K0. An array of doubles truncated to long is one VCVTTSD2SI per element from memory at -v3 and the packed VCVTTPD2QQ at -v4, where (unsigned)x also becomes VCVTTSD2USI.

AMD’s latency spreadsheet for Zen 5 gives the VEX and EVEX rows two macro-ops each, and a latency of 4 cycles only in the EVEX row.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src2.f64[0]
dest.write(cvtt_int(a, dest.bits))  # r32: bits 63:32 cleared
# {sae}: no exception flags

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTSD2SI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VCMPPD
• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS

All 253 AVX instructions

More AVX10.1 instructions

• VCVTSI2SH
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SH
• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS

All 686 AVX10.1 instructions