VCVTTSD2SIS

VCVTTSD2SIS converts the low double of a register or eight bytes of memory to a signed integer in a general-purpose register, truncating toward zero, and saturates where VCVTTSD2SI gives the integer indefinite: too large a value becomes the largest integer, 7FFFFFFFh or 7FFFFFFFFFFFFFFFh, too small a value the smallest, and a NaN 0. EVEX.W chooses a 32-bit or, in 64-bit mode, a 64-bit result; outside 64-bit mode W is ignored. It belongs to AVX10.2: opcode 6Dh in EVEX map 5 with an F2 prefix, where VCVTTSD2SI uses 2Ch in map 0F, and it accepts {sae} but no write mask. NaNs, infinities and out-of-range values still set IE, and a lost fraction sets PE. VCVTTSS2SIS converts a single, and VCVTTSD2USIS to an unsigned integer.

What it replaces#

C leaves out-of-range conversions undefined, but Rust’s as and

WebAssembly’s trunc_sat define them as saturating, and

VCVTTPS2DQS’s page explains the fix-up those

languages need without it. Clang 23 at -O2 with -mavx10.2 compiles

the C version of that rule, `x != x ? 0 : x >= 2147483647.0 ? INT_MAX

x <= -2147483648.0 ? INT_MIN : (int)x`, to VUCOMISD, two branches, VMAXSD and VCVTTSD2SI rather than to this one instruction.

In our builds#

GCC 14 has no AVX10.2 option. In Clang 23, _mm_cvtts_roundsd_i32(x, _MM_FROUND_NO_EXC) gives vcvttsd2sis eax, xmm0, {sae} and _mm_cvtts_roundsd_i64 the 64-bit form with RAX; (int)x stays VCVTTSD2SI. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src2.f64[0]
dest.write(cvtts_int(a, dest.bits))  # r32: bits 63:32 cleared
# {sae}: no exception flags

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTSD2SIS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCVTPH2HF8
• VCVTPH2HF8S
• VCVTPH2IBS
• VCVTPH2IUBS
• VCVTPS2IBS
• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2USIS
• VCVTTSS2SIS
• VCVTTSS2USIS
• VDIVBF16
• VDPPHPS
• VFMADD132BF16
• VFMADD213BF16
• VFMADD231BF16
• VFMSUB132BF16
• VFMSUB213BF16
• VFMSUB231BF16
• VFNMADD132BF16
• VFNMADD213BF16
• VFNMADD231BF16
• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16

All 96 AVX10.2 instructions