VCVTTSD2USI instruction (AVX10.1)

VCVTTSD2USI truncates the low double of an XMM register, or eight bytes of memory, toward zero to an unsigned integer in a 32-bit or 64-bit general-purpose register: C’s conversion from double to unsigned or uint64_t. It is the double-precision sibling of VCVTTSS2USI and the unsigned partner of VCVTTSD2SI, with all ones as the indefinite value instead of the top bit alone. It is EVEX only, from AVX512F on; the register form takes {sae}.

Recorded on Zen 5

The 32-bit edge. 2^31 minus a tiny fraction gave 7FFFFFFFh: a double holds values between integers this large, and truncation drops the fraction.
Indefinite without a flag. Negative infinity, with {sae} and IE unmasked in MXCSR, gave FFFFFFFFh in ESI without a fault and without IE.
Small values. 2.5 gave 2 and the smallest normal double, 2^-1022, gave 0; both set PE.

In compiled code

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile (unsigned)x of a double to vcvttsd2usi eax, xmm0 and (uint64_t)x to the form with RAX. Without AVX-512 they fall back as for singles: (unsigned)x is the 64-bit signed VCVTTSD2SI, and (uint64_t)x is a compare with 2^63 and a branch in GCC, two conversions and a select on the sign in Clang. _mm_cvttsd_u64 is the RAX form.

AMD’s Zen 5 latency spreadsheet gives two macro-ops, on pipes FP2/3 and FP4/5, and 4 cycles, as for VCVTTSS2USI.

Forms

Every encoding of VCVTTSD2USI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VCVTTSD2USI r32, xmm, {sae}` VCVTTSD2USI_GPR32u32_XMMf64_AVX512	`EVEX.LIG.F2.0F.W0 78 /r`	AVX10.1 or AVX512F
`VCVTTSD2USI r32, m64` VCVTTSD2USI_GPR32u32_MEMf64_AVX512	`EVEX.LIG.F2.0F.W0 78 /r`	AVX10.1 or AVX512F
`VCVTTSD2USI r64, xmm, {sae}` 64-bit mode only VCVTTSD2USI_GPR64u64_XMMf64_AVX512	`EVEX.LIG.F2.0F.W1 78 /r`	AVX10.1 or AVX512F
`VCVTTSD2USI r64, m64` 64-bit mode only VCVTTSD2USI_GPR64u64_MEMf64_AVX512	`EVEX.LIG.F2.0F.W1 78 /r`	AVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`r32, xmm, {sae}` `r64, xmm, {sae}`	`r32, m64`	`r64, m64`
Skylake-SP, Ice Lake	6 / 1p01	12 / 1p01	11 / 1p01
Sapphire Rapids	7 / 1p01	26 / 1p01	12 / 1p01
Zen 4	1 / 0.5FP2 FP3	8 / 0.5FP2 FP3	8 / 0.5FP2 FP3

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low double of xmm2 is converted, and the integer goes to r32.

r32 receives the conversion of double 0 of xmm2: r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src2.f64[0]
dest.write(cvtt_uint(a, dest.bits))  # r32: bits 63:32 cleared
# {sae}: no exception flags

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VCVTTSD2USI r32, xmm/m64, {sae}` `VCVTTSD2USI r64, xmm/m64, {sae}` 64-bit mode only
`r32/64`	explicit	write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTSD2USI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtt_roundsd_u32` `unsigned int _mm_cvtt_roundsd_u32(__m128d A, const int R)`	`VCVTTSD2USI r32, xmm, {sae}` EVEX.LIG -mavx512f
`_mm_cvtt_roundsd_u64` `unsigned long long _mm_cvtt_roundsd_u64(__m128d A, const int R)`	`VCVTTSD2USI r64, xmm, {sae}` EVEX.LIG -mavx512f
`_mm_cvttsd_u32` `unsigned int _mm_cvttsd_u32(__m128d __A)`	`VCVTTSD2USI r32, xmm` EVEX.LIG -mavx512f
`_mm_cvttsd_u64` `unsigned long long _mm_cvttsd_u64(__m128d __A)`	`VCVTTSD2USI r64, xmm` EVEX.LIG -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512F_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

AVX512F_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Recorded on Zen 5#

In compiled code#