x86-64.net

Instruction

VCVTTSH2SI

Converts the low half-precision value to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero.

Extensions
Forms
4 (4 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTTSH2SI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTTSH2SI r32, xmm, {sae} VCVTTSH2SI_GPR32i32_XMMf16_AVX512EVEX.LIG.F3.MAP5.W0 2C /rAVX10.1 or AVX512_FP16
VCVTTSH2SI r32, m16 VCVTTSH2SI_GPR32i32_MEMf16_AVX512EVEX.LIG.F3.MAP5.W0 2C /rAVX10.1 or AVX512_FP16
VCVTTSH2SI r64, xmm, {sae} 64-bit mode only VCVTTSH2SI_GPR64i64_XMMf16_AVX512EVEX.LIG.F3.MAP5.W1 2C /rAVX10.1 or AVX512_FP16
VCVTTSH2SI r64, m16 64-bit mode only VCVTTSH2SI_GPR64i64_MEMf16_AVX512EVEX.LIG.F3.MAP5.W1 2C /rAVX10.1 or AVX512_FP16

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTSH2SI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtt_roundsh_i32 int _mm_cvtt_roundsh_i32(__m128h A, const int R)

VCVTTSH2SI r32, xmm, {sae} EVEX.LIG -mavx512fp16

_mm_cvtt_roundsh_i64 long long _mm_cvtt_roundsh_i64(__m128h A, const int R)

VCVTTSH2SI r64, xmm, {sae} EVEX.LIG -mavx512fp16

_mm_cvttsh_i32 int _mm_cvttsh_i32(__m128h __A)

VCVTTSH2SI r32, xmm EVEX.LIG -mavx512fp16

_mm_cvttsh_i64 long long _mm_cvttsh_i64(__m128h __A)

VCVTTSH2SI r64, xmm EVEX.LIG -mavx512fp16

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_FP16_SCALAR

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.