Instruction
VCVTTSS2SI
Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero.
- Extensions
- Forms
- 8 (4 VEX, 4 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VCVTTSS2SI r32, m32
VCVTTSS2SI_GPR32d_MEMd | VEX.LIG.F3.0F.W0 2C /r | AVX |
VCVTTSS2SI r32, xmm
VCVTTSS2SI_GPR32d_XMMd | VEX.LIG.F3.0F.W0 2C /r | AVX |
VCVTTSS2SI r64, m32 64-bit mode only
VCVTTSS2SI_GPR64q_MEMd | VEX.LIG.F3.0F.W1 2C /r | AVX |
VCVTTSS2SI r64, xmm 64-bit mode only
VCVTTSS2SI_GPR64q_XMMd | VEX.LIG.F3.0F.W1 2C /r | AVX |
VCVTTSS2SI r32, xmm, {sae}
VCVTTSS2SI_GPR32i32_XMMf32_AVX512 | EVEX.LIG.F3.0F.W0 2C /r | AVX10.1 or AVX512F |
VCVTTSS2SI r32, m32
VCVTTSS2SI_GPR32i32_MEMf32_AVX512 | EVEX.LIG.F3.0F.W0 2C /r | AVX10.1 or AVX512F |
VCVTTSS2SI r64, xmm, {sae} 64-bit mode only
VCVTTSS2SI_GPR64i64_XMMf32_AVX512 | EVEX.LIG.F3.0F.W1 2C /r | AVX10.1 or AVX512F |
VCVTTSS2SI r64, m32 64-bit mode only
VCVTTSS2SI_GPR64i64_MEMf32_AVX512 | EVEX.LIG.F3.0F.W1 2C /r | AVX10.1 or AVX512F |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VCVTTSS2SI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_cvtt_roundss_i32
int _mm_cvtt_roundss_i32(__m128 A, const int R) |
|
_mm_cvtt_roundss_i64
long long _mm_cvtt_roundss_i64(__m128 A, const int R) |
|
_mm_cvtt_roundss_si32
int _mm_cvtt_roundss_si32(__m128 A, const int R) |
|
_mm_cvtt_roundss_si64
long long _mm_cvtt_roundss_si64(__m128 A, const int R) |
|
_mm_cvtt_ss2si
int _mm_cvtt_ss2si(__m128 __a) |
|
_mm_cvttss_i32
int _mm_cvttss_i32(__m128 __A) |
|
_mm_cvttss_i64
long long _mm_cvttss_i64(__m128 __A) |
|
_mm_cvttss_si32
int _mm_cvttss_si32(__m128 __a) |
|
_mm_cvttss_si64
long long _mm_cvttss_si64(__m128 __a) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX | AVX | Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2 |
AVX512F_SCALAR | AVX10.1 or AVX512F | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill |
More AVX10.1 instructions
- VCVTSS2SI
- VCVTSS2USI
- VCVTTPD2DQ
- VCVTTPD2QQ
- VCVTTPD2UDQ
- VCVTTPD2UQQ
- VCVTTPH2DQ
- VCVTTPH2QQ
- VCVTTPH2UDQ
- VCVTTPH2UQQ
- VCVTTPH2UW
- VCVTTPH2W
- VCVTTPS2DQ
- VCVTTPS2QQ
- VCVTTPS2UDQ
- VCVTTPS2UQQ
- VCVTTSD2SI
- VCVTTSD2USI
- VCVTTSH2SI
- VCVTTSH2USI
- VCVTTSS2USI
- VCVTUDQ2PD
- VCVTUDQ2PH
- VCVTUDQ2PS
- VCVTUQQ2PD
- VCVTUQQ2PH
- VCVTUQQ2PS
- VCVTUSI2SD
- VCVTUSI2SH
- VCVTUSI2SS
- VCVTUW2PH
- VCVTW2PH
- VDBPSADBW
- VDIVPD
- VDIVPH
- VDIVPS
- VDIVSD
- VDIVSH
- VDIVSS
- VDPBF16PS
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.