VCVTTSS2SI

VCVTTSS2SI is CVTTSS2SI in VEX and EVEX encodings: the low single of an XMM register or of four bytes of memory, truncated toward zero to a signed integer in a 32-bit or 64-bit general-purpose register. CVTTSS2SI’s page covers the truncation, the integer indefinite value and the unsigned conversions. The destination is a general-purpose register, so the new encodings add no third operand and no zeroing of a vector register; VEX.vvvv and EVEX.vvvv must be 1111b. The VEX form needs AVX. The EVEX form, with AVX-512F or AVX10.1, can reach XMM16 to XMM31 and adds {sae}, which keeps IE and PE from being reported; it has no rounding mode, since the T fixes the rounding.

Recorded on Zen 5#

• vcvttss2si r9d, xmm8 truncated -2.5 to -2 (FFFFFFFEh in R9, the upper half cleared) under MXCSR 3FC0h, which asks for rounding down, and set PE.
• {evex} vcvttss2si r14d, xmm17, {sae} truncated the same -2.5 to -2 and left MXCSR at 1E40h, without PE.
• {evex} vcvttss2si r14, xmm0, {sae} turned 10^30 into the indefinite 8000000000000000h, and MXCSR 1E40h, whose invalid exception is unmasked, gave no #XM and no IE.
• The 32-bit form gave 80000000h for 2^63 and set IE.

In compiled code#

In our builds at -O2 with -march=x86-64-v3 or -v4, (int)x of a float is vcvttss2si eax, xmm0 and (long)x the form with RAX. An array of floats truncated to long stays scalar at -v3: GCC 14 converts each element from memory, Clang 23 also gathers pairs with VMOVQ and VPUNPCKLQDQ for wide stores. At -march=x86-64-v4 both use the packed VCVTTPS2QQ, and (unsigned)x becomes VCVTTSS2USI instead of the 64-bit conversion. _mm_cvtt_roundss_i32(a, _MM_FROUND_NO_EXC) gives the {sae} form.

AMD’s latency spreadsheet for Zen 5 gives two macro-ops on pipes FP2/3 and FP4/5 in both rows, and a latency of 4 cycles only in the EVEX row; the VEX row, like CVTTSS2SI’s, lists none.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src2.f32[0]
dest.write(cvtt_int(a, dest.bits))  # r32: bits 63:32 cleared
# {sae}: no exception flags

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTSS2SI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VCMPPS
• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS
• VMAXPD

All 253 AVX instructions

More AVX10.1 instructions

• VCVTSS2SI
• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS

All 686 AVX10.1 instructions