x86-64.net

Instruction

VCVTTSS2SIS

Converts the low single to a signed 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN.

Extensions
Forms
4 (4 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VCVTTSS2SIS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VCVTTSS2SIS r32, xmm, {sae} VCVTTSS2SIS_GPR32i32_XMMf32_AVX512EVEX.LIG.F3.MAP5.W0 6D /rAVX10.2
VCVTTSS2SIS r32, m32 VCVTTSS2SIS_GPR32i32_MEMf32_AVX512EVEX.LIG.F3.MAP5.W0 6D /rAVX10.2
VCVTTSS2SIS r64, xmm, {sae} 64-bit mode only VCVTTSS2SIS_GPR64i64_XMMf32_AVX512EVEX.LIG.F3.MAP5.W1 6D /rAVX10.2
VCVTTSS2SIS r64, m32 64-bit mode only VCVTTSS2SIS_GPR64i64_MEMf32_AVX512EVEX.LIG.F3.MAP5.W1 6D /rAVX10.2

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTSS2SIS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtts_roundss_i32 int _mm_cvtts_roundss_i32(__m128 __A, const int __R)

VCVTTSS2SIS r32, xmm, {sae} EVEX.LIG -mavx10.2

_mm_cvtts_roundss_i64 long long _mm_cvtts_roundss_i64(__m128 __A, const int __R)

VCVTTSS2SIS r64, xmm, {sae} EVEX.LIG -mavx10.2

_mm_cvtts_roundss_si32 int _mm_cvtts_roundss_si32(__m128 __A, const int __R)

VCVTTSS2SIS r32, xmm, {sae} EVEX.LIG -mavx10.2

_mm_cvtts_roundss_si64 long long _mm_cvtts_roundss_si64(__m128 __A, const int __R)

VCVTTSS2SIS r64, xmm, {sae} EVEX.LIG -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_SAT_CVT_DS_SCALAR

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.