VCVTTSS2SIS instruction (AVX10.2)

VCVTTSS2SIS converts the low single of a register or four bytes of memory to a signed integer in a general-purpose register, truncating toward zero and saturating: too large a value gives 7FFFFFFFh, or 7FFFFFFFFFFFFFFFh for a 64-bit result, too small a value gives the smallest integer, and a NaN gives 0, where VCVTTSS2SI returns the integer indefinite for all of them. EVEX.W chooses the width in 64-bit mode and is ignored elsewhere. It belongs to AVX10.2: opcode 6Dh in EVEX map 5 with an F3 prefix, the double version VCVTTSD2SIS having F2, with {sae} and no write mask. NaNs, infinities and out-of-range values still set IE, and a lost fraction sets PE. VCVTTSS2USIS converts to an unsigned integer and VCVTTPS2DQS a vector of singles.

In our builds

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles _mm_cvtts_roundss_i32(x, _MM_FROUND_CUR_DIRECTION) to vcvttss2sis eax, xmm0, while (long)x on a float stays VCVTTSS2SI, so code that wants the saturating result has to ask for it through the intrinsic. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Every encoding of VCVTTSS2SIS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VCVTTSS2SIS r32, xmm, {sae}` VCVTTSS2SIS_GPR32i32_XMMf32_AVX512	`EVEX.LIG.F3.MAP5.W0 6D /r`	AVX10.2
`VCVTTSS2SIS r32, m32` VCVTTSS2SIS_GPR32i32_MEMf32_AVX512	`EVEX.LIG.F3.MAP5.W0 6D /r`	AVX10.2
`VCVTTSS2SIS r64, xmm, {sae}` 64-bit mode only VCVTTSS2SIS_GPR64i64_XMMf32_AVX512	`EVEX.LIG.F3.MAP5.W1 6D /r`	AVX10.2
`VCVTTSS2SIS r64, m32` 64-bit mode only VCVTTSS2SIS_GPR64i64_MEMf32_AVX512	`EVEX.LIG.F3.MAP5.W1 6D /r`	AVX10.2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low single of xmm2 is converted, and the integer goes to r32.

r32 receives the conversion of single 0 of xmm2: r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src2.f32[0]
dest.write(cvtts_int(a, dest.bits))  # r32: bits 63:32 cleared
# {sae}: no exception flags

Not run on a processor: none of these processors has AVX10.2.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VCVTTSS2SIS r32, xmm/m32, {sae}` `VCVTTSS2SIS r64, xmm/m32, {sae}` 64-bit mode only
`r32/64`	explicit	write
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTSS2SIS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtts_roundss_i32` `int _mm_cvtts_roundss_i32(__m128 __A, const int __R)`	`VCVTTSS2SIS r32, xmm, {sae}` EVEX.LIG -mavx10.2
`_mm_cvtts_roundss_i64` `long long _mm_cvtts_roundss_i64(__m128 __A, const int __R)`	`VCVTTSS2SIS r64, xmm, {sae}` EVEX.LIG -mavx10.2
`_mm_cvtts_roundss_si32` `int _mm_cvtts_roundss_si32(__m128 __A, const int __R)`	`VCVTTSS2SIS r32, xmm, {sae}` EVEX.LIG -mavx10.2
`_mm_cvtts_roundss_si64` `long long _mm_cvtts_roundss_si64(__m128 __A, const int __R)`	`VCVTTSS2SIS r64, xmm, {sae}` EVEX.LIG -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX512_SAT_CVT_DS_SCALAR` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

In our builds#