VCVTTSS2USI

VCVTTSS2USI truncates the low single of an XMM register, or four bytes of memory, toward zero to an unsigned integer in a 32-bit or 64-bit general-purpose register: C’s conversion from float to unsigned or uint64_t. It is the unsigned partner of VCVTTSS2SI, whose page covers the EVEX encoding and {sae}; it exists only as an EVEX instruction, from AVX512F on. The valid range is 0 to 2^32 - 1 or 2^64 - 1, and the indefinite value for anything outside it, negative numbers at or below -1 included, is the largest unsigned value, all ones. A 32-bit destination clears bits 63:32 of the register. VCVTTSD2USI is the double-precision form.

Recorded on Zen 5#

• Past the signed range. 2^31 from memory gave 80000000h in ECX without setting IE: the bits that the signed conversion returns as its indefinite, here a valid result. 2^32 gave 100000000h in R9.
• Truncation. 2.5 gave 2 in EDX with {sae}, which left MXCSR as it was. 2,147,483,520.0, the largest single below 2^31, gave 7FFFFF80h in RAX.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile (unsigned)x of a float to vcvttss2usi eax, xmm0 and (uint64_t)x to the form with RAX. With -march=x86-64-v3, (unsigned)x is the signed 64-bit VCVTTSS2SI into RAX, whose low half holds every result in range. (uint64_t)x has no wider signed conversion to use: GCC compares x with 2^63 and branches to a path that subtracts it before the conversion and flips bit 63 after it with BTC, while Clang converts both x and x - 2^63 and selects with the sign of the first result, without a branch. _mm_cvttss_u32 is one VCVTTSS2USI.

AMD’s Zen 5 latency spreadsheet gives two macro-ops, on pipes FP2/3 and FP4/5, and 4 cycles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src2.f32[0]
dest.write(cvtt_uint(a, dest.bits))  # r32: bits 63:32 cleared
# {sae}: no exception flags

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTTSS2USI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTSS2USI
• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD

All 686 AVX10.1 instructions