VCVTUDQ2PD

VCVTUDQ2PD converts unsigned doublewords to doubles: 8 from a YMM register or memory fill a ZMM register, 4 fill a YMM register and 2 an XMM register. A double has a 53-bit significand, so every 32-bit unsigned integer converts exactly; the instruction never rounds and sets no MXCSR flag. It is the unsigned partner of VCVTDQ2PD, and the difference shows from 80000000h up: VCVTDQ2PD reads that as -2^31, VCVTUDQ2PD as 2^31. VCVTUDQ2PS converts the same input to singles, which do round. It came with AVX512F.

Recorded on Zen 5#

• Exact values. 80000000h gave 2^31, 7FFFFFFFh gave 2,147,483,647.0, and 01000001h and 01000003h, which singles cannot hold, gave 16,777,217.0 and 16,777,219.0. MXCSR stayed as it was in all six cases.
• One register both ways. In vcvtudq2pd zmm9{k1}, ymm9, elements 5 and 7, selected by K1, became 1.0 and 2^31 from doublewords 1 and 80000000h, and the unselected elements, which hold the source doublewords, kept their bits.
• Zeroing. A broadcast of 01000003h to XMM9 under a zero mask that selected both elements gave two copies, and the register was cleared above bit 127.

In compiled code#

At -O2 with -march=x86-64-v4, Clang 23 compiles d[i] = u[i] from uint32_t to double into VCVTUDQ2PD from memory on YMM registers. GCC 14 does not use it: it converts with the signed VCVTDQ2PD and adds 2^32 under a mask where the result is negative, found with VCMPPD. _mm512_cvtepu32_pd is one VCVTUDQ2PD in both.

AMD’s Zen 5 latency spreadsheet gives the XMM form one macro-op and 3 cycles, the YMM form from a register two macro-ops and 4 cycles but from memory one and 3, and the ZMM form two macro-ops and 6 cycles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.f64[i] = to_f64(src2.d[i])
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m32bcst: src2.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E5

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Half); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTUDQ2PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTTPD2DQ
• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS

All 686 AVX10.1 instructions