VCVTUDQ2PH

VCVTUDQ2PH converts unsigned doublewords to half precision, the vector form of C’s conversion from unsigned int to _Float16. It is the unsigned partner of VCVTDQ2PH, whose page covers the widths, the rounding and where a half runs out: 16 doublewords of a ZMM register become 16 halves in a YMM register, and so on down to 4 halves in the low 64 bits of an XMM register. The opcode is 7Ah with the F2 prefix in EVEX map 5, the byte of VCVTUDQ2PS in the 0F map.

Where signed and unsigned part#

The two conversions agree up to 7FFFFFFFh, and that range already ends far past a half’s largest finite value, 65504: in round to nearest every input from 65520 up becomes infinity, toward zero it becomes 65504, and Intel’s entry lists overflow and precision for both. From 80000000h on, VCVTDQ2PH reads a negative number and gives minus infinity or -65504, where VCVTUDQ2PH gives plus infinity or 65504. Like the other AVX512-FP16 conversions it takes a write mask with merging or zeroing, a doubleword broadcast from memory, and {er} on the 512-bit register form.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, h[i] = u[i] from a uint32_t array to a _Float16 array becomes VCVTUDQ2PH from memory in GCC 14 and Clang 23, with the same arrangement as VCVTDQ2PH: two ZMM loads joined into one ZMM store in GCC, YMM loads to XMM results in Clang. A single value is converted with VCVTUSI2SH. At -march=x86-64-v3, without AVX512-FP16, Clang builds a single from the two 16-bit halves of each element with VPBLENDW, VSUBPS and VADDPS, as on the VCVTUDQ2PS page, and narrows it with VCVTPS2PH; GCC zero-extends each element to 64 bits, converts it to a double and calls __truncdfhf2. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTUDQ2PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        ymm1.f16[i] = to_f16(src2.d[i])
    elif zeroing:
        ymm1.f16[i] = 0
    # else: ymm1.f16[i] keeps its value
for i in range(VL // 32, 8):
    ymm1.w[i] = 0
# m32bcst: src2.d[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTUDQ2PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTTPD2QQ
• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4

All 686 AVX10.1 instructions