VCVTUDQ2PS

VCVTUDQ2PS converts unsigned doublewords to singles, 4, 8 or 16 at a time. It is the unsigned partner of CVTDQ2PS, whose page explains the rounding of integers above 2^24 and the workarounds for unsigned input before AVX-512; this one needs none of them. The difference shows from 80000000h up: VCVTDQ2PS reads FFFFFFFFh as -1 and gives -1.0, VCVTUDQ2PS reads it as 4,294,967,295.

Rounding near the top#

That largest input lies between two singles, 4,294,967,040 (4F7FFFFFh) and 2^32, so the rounding mode decides, and a result of 2^32 is outside the range of uint32_t when converted back. The cases recorded on Zen 5 show the modes at work:

• FFFFFFFFh and FFFFFFFEh rounded toward zero or down gave 4,294,967,040;
• 7FFFFFFFh rounded up gave 2^31, and 01000001h (2^24 + 1) rounded up gave 2^24 + 2;
• 80000000h, FFFFFFh and 1 converted exactly.

The inexact ones set PE. The 512-bit register form takes {er}, a rounding mode for this instruction alone that also keeps MXCSR’s flags as they are: a recorded case with {rz-sae} left MXCSR unchanged. Like other AVX-512 conversions it takes a write mask with merging or zeroing, and a 32-bit broadcast from memory.

In compiled code#

For d[i] = a[i] from uint32_t to float, Clang 23 at -O2 with -march=x86-64-v4 emits one VCVTUDQ2PS per 8 elements on YMM registers, and VCVTUSI2SS for the last few. With -march=x86-64-v3 it builds the result from the two 16-bit halves of each element with VPBLENDW, VSUBPS and VADDPS, the AVX2 version of the trick on the CVTDQ2PS page. GCC 14 keeps the loop scalar at -O2, with one VCVTUSI2SS per element under x86-64-v4. The intrinsics are _mm512_cvtepu32_ps and its masked, rounding and narrower kin.

VCVTUDQ2PD converts to doubles, which hold every 32-bit integer exactly, and VCVTPS2UDQ goes the other way.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        zmm1.f32[i] = to_f32(src2.d[i])
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m32bcst: src2.d[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTUDQ2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTTPD2UDQ
• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8

All 686 AVX10.1 instructions