VCVTUQQ2PD

VCVTUQQ2PD converts each unsigned quadword of an XMM, YMM or ZMM register, or of memory, to a double: the vector form of C’s conversion from uint64_t to double. It is the unsigned partner of VCVTQQ2PD, whose page covers the rounding, and came with it in AVX512DQ; VCVTUQQ2PS converts to singles. The difference from the signed form is the top bit: 8000000000000000h is 2^63 here, and the largest input is 2^64 - 1. A double holds every integer up to 2^53 exactly; a larger one is rounded as MXCSR.RC says or, in the 512-bit register form, as the {er} operand says, and an inexact result sets PE, the only exception it can raise.

Recorded on Zen 5#

• Up. With MXCSR rounding up, 2^63 - 513 gave 2^63 and set PE, while 2^32 - 1 converted exactly.
• Down. 8000000000000001h, 2^63 + 1, gave 2^63 and set PE.
• Toward zero. FFFFFFFFFFFFFFFEh gave 2^64 - 2048, the largest double below 2^64, and 2^63 - 513 gave 2^63 - 1024.
• An override. Under {rn-sae}, 2^64 - 1 gave 2^64 and 2^63 - 1 gave 2^63, while 1 and 2^24 + 3 converted exactly; MXCSR stayed unchanged.

In compiled code#

At -O2 with -march=x86-64-v4, both compilers vectorize d[i] = (double)u[i] over uint64_t with VCVTUQQ2PD straight from memory, GCC 14 on ZMM registers and Clang 23 on YMM registers. A single conversion is VCVTUSI2SD. The intrinsic is _mm512_cvtepu64_pd; the SDM’s list for this entry names it _mm512_cvtepu64_ps, with a __m512d result.

AMD’s Zen 5 latency spreadsheet gives every width one macro-op on pipe FP2 or FP3 and 3 cycles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.f64[i] = to_f64(src2.q[i])
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m64bcst: src2.q[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTUQQ2PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTTPD2UQQ
• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2

All 686 AVX10.1 instructions