VCVTUQQ2PH

VCVTUQQ2PH converts unsigned quadwords to half precision: 8, 4 or 2 of them from a ZMM, YMM or XMM register or memory into the low 128, 64 or 32 bits of an XMM register, clearing the rest. It is the unsigned partner of VCVTQQ2PH, whose page covers the widths, and of VCVTUQQ2PS for singles; the opcode is 7Ah with the F2 prefix and W1 in EVEX map 5, where VCVTUDQ2PH has W0.

Signed and unsigned#

The two agree from 0 to 2^63 - 1, a range in which every value from 65520 up overflows to infinity in round to nearest and becomes 65504 toward zero; Intel’s entry lists overflow and precision. The top half of the range is where they part: VCVTQQ2PH reads FFFFFFFFFFFFFFFFh as -1 and gives -1.0, VCVTUQQ2PH reads it as 2^64 - 1 and overflows. The rounding mode comes from MXCSR.RC, or from {er} on the 512-bit register form, and a quadword can be broadcast from memory.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, Clang 23 converts a uint64_t array into a _Float16 array with VCVTUQQ2PH from YMM loads, joining the XMM results with VINSERTF128 and VUNPCKLPD as for VCVTQQ2PH. GCC 14 stays scalar, one VCVTUSI2SH from memory per element. Without AVX512-FP16, at -march=x86-64-v3, GCC loads each quadword with the x87 FILD, adds 2^64 when the sign bit was set, and calls the library’s __truncxfhf2. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTUQQ2PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        xmm1.f16[i] = to_f16(src2.q[i])
    elif zeroing:
        xmm1.f16[i] = 0
    # else: xmm1.f16[i] keeps its value
for i in range(VL // 64, 8):
    xmm1.w[i] = 0
# m64bcst: src2.q[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTUQQ2PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTTPH2DQ
• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4

All 686 AVX10.1 instructions