VCVTUQQ2PS

VCVTUQQ2PS converts unsigned quadwords to singles, the result half as wide as the source: 8 quadwords of a ZMM register become 8 singles in a YMM register, 4 fill an XMM register and 2 its low 64 bits, with the rest cleared. It is the unsigned partner of VCVTQQ2PS, whose page covers the width and the masks; the difference is the meaning of the top bit. 8000000000000000h is -2^63 to VCVTQQ2PS and 2^63 here, and the largest input is 2^64 - 1. It came with AVX512DQ, as did VCVTUQQ2PD, which converts to doubles.

Rounding on Zen 5#

A single has a 24-bit significand, so only integers up to 2^24 are sure to convert exactly, and the rounding mode decides the rest:

• Up. With MXCSR rounding up, 2^24 + 1 and 2^24 + 3 gave 2^24 + 2 and 2^24 + 4, and set PE.
• Down. 2^63 - 1 gave 2^63 - 2^39, the largest single below 2^63, and 2^24 + 3 gave 2^24 + 2.
• Past 2^63. Under {ru-sae}, 2^64 - 2 and 2^64 - 1 both gave 2^64, a single no uint64_t can hold, while 0 and 1 converted exactly; MXCSR stayed unchanged.
• The top bit. A broadcast of 8000000000000000h gave 2^63 in every selected element.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile f[i] = (float)uq[i] from uint64_t to VCVTUQQ2PS from memory, GCC on ZMM loads joined with VINSERTF32X8, Clang on YMM loads into XMM results. With -march=x86-64-v3, GCC converts one element at a time: a value with the top bit set is halved, its low bit kept, converted with the signed VCVTSI2SS and doubled with VADDSS. Clang does the same four elements at a time with VPSRLQ, VPOR and VBLENDVPD, but still converts each element on its own. _mm512_cvtepu64_ps is one VCVTUQQ2PS.

AMD’s Zen 5 latency spreadsheet gives one macro-op and 3 cycles from an XMM source, and two macro-ops with 6 and 7 cycles from YMM and ZMM sources, as for VCVTQQ2PS.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        ymm1.f32[i] = to_f32(src2.q[i])
    elif zeroing:
        ymm1.f32[i] = 0
    # else: ymm1.f32[i] keeps its value
for i in range(VL // 64, 4):
    ymm1.d[i] = 0
# m64bcst: src2.q[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTUQQ2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTTPH2QQ
• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4

All 686 AVX10.1 instructions