VCVTUSI2SD

VCVTUSI2SD converts an unsigned integer of 32 or 64 bits, from a general-purpose register or memory, to a double in the low element of an XMM register; bits 127:64 come from the first source and the register is cleared from bit 128 up. It is the double-precision sibling of VCVTUSI2SS, whose page describes the merge with the first source, the wait that it causes and how the compilers avoid it; all of that applies here too.

Two sizes, one exact#

A double has a 53-bit significand, so every 32-bit integer converts exactly. The 32-bit form therefore never sets PE and has no {er} operand, while the 64-bit form has one, and rounds values above 2^53 that do not fit. In the cases recorded on Zen 5:

• vcvtusi2sd xmm17, xmm30, edx with RDX = 891D269701000001h gave 16,777,217.0: the 32-bit form reads EDX only, and the upper half of RDX does not matter.
• The quadword FFF0000000000001h from memory, 2^64 - 2^52 + 1, became 2^64 - 2^52 with MXCSR rounding toward zero, and set PE. Read as a double, those bytes would be a NaN; the instruction reads an integer and never sees one.
• Zero converted under {ru-sae} gave +0.0 and left MXCSR unchanged.

The largest input, 2^64 - 1, rounds to 2^64 to nearest, a value that no uint64_t can hold when converted back.

Unsigned before and with AVX-512#

Before AVX-512, converting uint32_t to double needs no unsigned instruction: GCC 14 and Clang 23 at -O2 zero-extend the value to 64 bits and use the signed 64-bit CVTSI2SD, whose page also shows the longer sequences for uint64_t. With -march=x86-64-v4 both compilers emit VCVTUSI2SD for either size, as vcvtusi2sd xmm0, xmm0, edi in GCC and with XMM15 as the first source in Clang. The intrinsics are _mm_cvtu32_sd, _mm_cvtu64_sd and _mm_cvt_roundu64_sd; there is no rounding variant for 32 bits. The 64-bit forms exist only in 64-bit mode.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f64[0] = to_f64(src3.read())
xmm1.q[1] = xmm2.q[1]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Forms only in 64-bit mode

AVX512-E3NF

Other forms

AVX512-E10NF

Attributes

What else XED records about the forms. How to read.

Forms only in 64-bit mode

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTUSI2SD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTTPH2UDQ
• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8

All 686 AVX10.1 instructions