VCVTUSI2SH

VCVTUSI2SH converts an unsigned integer from a general-purpose register or memory, 32 bits or, with EVEX.W1 in 64-bit mode, 64 bits, to a half in the low 16 bits of the destination, copying bits 127:16 from the middle operand. It is the unsigned partner of VCVTSI2SH and the scalar form of VCVTUDQ2PH and VCVTUQQ2PH; the opcode is 7Bh with the F3 prefix in EVEX map 5, as for VCVTUSI2SS in the 0F map. Intel’s entry is titled for doublewords but also lists the quadword form.

Range#

Every unsigned value from 65520 up overflows a half in round to nearest, giving infinity with OE and PE, and becomes 65504 toward zero or down; Intel’s entry lists overflow and precision. The two partners differ only for inputs with the top bit set: VCVTSI2SH reads FFFFFFFFh as -1, VCVTUSI2SH as 4,294,967,295, which overflows. The rounding mode is MXCSR.RC or, for a register source, an {er} mode; there is no write mask.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile return x; from unsigned or unsigned long to _Float16 to VCVTUSI2SH with a 32- or 64-bit register, Clang again taking the upper bits from the otherwise unused XMM31. GCC also uses it, from memory, for each element of a uint64_t array converted to halves, where Clang uses VCVTUQQ2PH. Without AVX512-FP16, at -march=x86-64-v3, Clang converts an unsigned long with the top bit set by halving it, keeping the low bit, converting with VCVTSI2SS and doubling, and GCC loads it with the x87 FILD, adds 2^64 and calls __truncxfhf2. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTUSI2SH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f16[0] = to_f16(src3.read())
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTUSI2SH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTTPH2UQQ
• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2

All 686 AVX10.1 instructions