VCVTUSI2SS

VCVTUSI2SS converts an unsigned integer of 32 or 64 bits, from a general-purpose register or memory, to a single in the low element of an XMM register. Like the VEX form of CVTSI2SS, it takes elements 1 to 3 from its first source and clears bits 128 and up. It is part of AVX-512F, and the 64-bit forms exist only in 64-bit mode.

Both sizes round#

A single has a 24-bit significand, so even a 32-bit integer above 2^24 may not fit: such values are rounded as MXCSR.RC says and set PE. A register source can take an {er} operand that names the rounding for this one instruction and suppresses the flags, in both sizes; the double-precision VCVTUSI2SD has none in its 32-bit form, which is always exact. The cases recorded on Zen 5 include FFFFFFH, the largest integer below 2^24, converted exactly under {ru-sae}; 7FFFFFFFFFFFFFC0H under {rz-sae}, which became the largest single below 2^63; and 0080000080400000H from memory with MXCSR rounding toward zero, which became 2^55 and set PE.

Unsigned without AVX-512#

The SSE and AVX conversions take signed integers only, and GCC 14 and Clang 23 at -O2 work around that:

• For a 32-bit unsigned value, both zero-extend it to 64 bits and use the 64-bit form of CVTSI2SS, which rounds once and correctly.
• For a 64-bit one, GCC tests the sign bit; when it is set, it halves the value, ORs the lost bit back in so that the rounding comes out right, converts, and doubles the result with ADDSS.

With -march=x86-64-v4 both compilers emit VCVTUSI2SS for either size. The instruction merges into its first source, which makes it wait for the instruction that last wrote that register, as CVTSI2SD describes: GCC zeroes the destination with VXORPS and names it as the source, and Clang names XMM15, which its code never writes.

AMD’s Zen 5 guide lists the register form as two macro-ops and the memory form as one, each with a latency of three cycles. VCVTUDQ2PS converts packed unsigned doublewords.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f32[0] = to_f32(src3.read())
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3NF

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTUSI2SS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTTPH2UW
• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4

All 686 AVX10.1 instructions