VCVTUW2PH

VCVTUW2PH converts unsigned words to half precision, 8, 16 or 32 at a time, in a destination as wide as the source. It is the unsigned partner of VCVTW2PH, with the same opcode, 7Dh in EVEX map 5, under F2 instead of F3; VCVTUDQ2PH converts unsigned doublewords. VADDPH covers AVX512-FP16 and the format.

The top of the word range overflows#

Signed words always fit a half, so VCVTW2PH lists only the precision exception; unsigned words reach 65535, past the largest finite half, 65504, and Intel’s entry for VCVTUW2PH adds overflow. Above 32768 the halves are 32 apart: in round to nearest, 65519 becomes 65504, while 65520 lies halfway to 65536 and rounds to the even significand, which is past the format, so it and every word above become infinity with OE and PE set. Toward zero or down they become 65504. Intel’s optimization manual points out that full-range unsigned words land at the very top of the half range, where almost any arithmetic overflows, and advises scaling them after the conversion (Section 18.5.7).

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, h[i] = u[i] from a uint16_t array to a _Float16 array becomes VCVTUW2PH from memory in GCC 14, on ZMM registers, and Clang 23, on YMM registers. For a single unsigned short, GCC zero-extends it and uses VCVTUSI2SH, while Clang uses the signed VCVTSI2SH, which gives the same half for any value below 2^31. _mm512_cvtepu16_ph and _mm512_cvt_roundepu16_ph are the intrinsics. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTUW2PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        zmm1.f16[i] = to_f16(src2.w[i])
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src2.w[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTUW2PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTTPH2W
• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS

All 686 AVX10.1 instructions