VCVTW2PH

VCVTW2PH converts signed words to half precision, element for element: 8, 16 or 32 at a time, in a destination as wide as the source. No SSE or AVX conversion before AVX512-FP16 read 16-bit integers; only AMD’s 3DNow! extensions had one, PI2FW. The opcode is 7Dh with the F3 prefix in EVEX map 5; VCVTUW2PH is the same byte with F2 for unsigned words, and VCVTDQ2PH converts doublewords. VADDPH covers AVX512-FP16 and the format.

Rounded but never infinite#

Every signed word lies within a half’s range, whose largest finite value is 65504, so Intel’s entry lists only the precision exception: from 2049 up in magnitude a word may fall between two halves and is rounded by MXCSR.RC, or by an {er} mode on the 512-bit register form. Near the top the halves are 16 apart, so 32767 becomes 32768 in round to nearest and 32752 toward zero, while -32768 is exact. Intel’s optimization manual warns that such values leave little room before products overflow, and suggests scaling them after the conversion, by 1/256 for example (Sections 18.5.2 and 18.5.7).

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, h[i] = a[i] from an int16_t array to a _Float16 array becomes VCVTW2PH from memory in GCC 14, on ZMM registers, and Clang 23, on YMM registers; with the manual’s scaling, a[i] * (_Float16)(1.0 / 256), each conversion is followed by one VMULPH by a broadcast constant. _mm_cvtepi16_ph and its wider forms give the register form. The source can be one word broadcast from memory, but for _mm512_cvtepi16_ph(_mm512_set1_epi16(*p)) neither compiler used it: GCC broadcast the word with VPBROADCASTW first, Clang converted it and broadcast the half. A single short is widened to int and converted with VCVTSI2SH. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VCVTW2PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        zmm1.f16[i] = to_f16(src2.sw[i])
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src2.w[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VCVTW2PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTTPS2DQ
• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH

All 686 AVX10.1 instructions