x86-64.net

Instruction

VDBPSADBW

Sums absolute differences of 4-byte groups of the two sources into 16-bit results, after an immediate shuffles the second within each 128-bit lane.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VDBPSADBW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VDBPSADBW xmm {k}{z}, xmm, xmm, imm8 VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512EVEX.128.66.0F3A.W0 42 /r ibAVX10.1 or AVX512BW + AVX512VL
VDBPSADBW xmm {k}{z}, xmm, m128, imm8 VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512EVEX.128.66.0F3A.W0 42 /r ibAVX10.1 or AVX512BW + AVX512VL
VDBPSADBW ymm {k}{z}, ymm, ymm, imm8 VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512EVEX.256.66.0F3A.W0 42 /r ibAVX10.1 or AVX512BW + AVX512VL
VDBPSADBW ymm {k}{z}, ymm, m256, imm8 VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512EVEX.256.66.0F3A.W0 42 /r ibAVX10.1 or AVX512BW + AVX512VL
VDBPSADBW zmm {k}{z}, zmm, zmm, imm8 VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512EVEX.512.66.0F3A.W0 42 /r ibAVX10.1 or AVX512BW
VDBPSADBW zmm {k}{z}, zmm, m512, imm8 VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512EVEX.512.66.0F3A.W0 42 /r ibAVX10.1 or AVX512BW

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VDBPSADBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_dbsad_epu8 __m128i _mm_dbsad_epu8(__m128i A, __m128i B, const int imm)

VDBPSADBW xmm, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm_mask_dbsad_epu8 __m128i _mm_mask_dbsad_epu8(__m128i W, __mmask8 U, __m128i A, __m128i B, const int imm)

VDBPSADBW xmm {k}, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_dbsad_epu8 __m128i _mm_maskz_dbsad_epu8(__mmask8 U, __m128i A, __m128i B, const int imm)

VDBPSADBW xmm {k}{z}, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512bw

_mm256_dbsad_epu8 __m256i _mm256_dbsad_epu8(__m256i A, __m256i B, const int imm)

VDBPSADBW ymm, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm256_mask_dbsad_epu8 __m256i _mm256_mask_dbsad_epu8(__m256i W, __mmask16 U, __m256i A, __m256i B, const int imm)

VDBPSADBW ymm {k}, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_dbsad_epu8 __m256i _mm256_maskz_dbsad_epu8(__mmask16 U, __m256i A, __m256i B, const int imm)

VDBPSADBW ymm {k}{z}, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512bw

_mm512_dbsad_epu8 __m512i _mm512_dbsad_epu8(__m512i A, __m512i B, const int imm)

VDBPSADBW zmm, zmm, zmm, imm8 EVEX.512 -mavx512bw

_mm512_mask_dbsad_epu8 __m512i _mm512_mask_dbsad_epu8(__m512i W, __mmask32 U, __m512i A, __m512i B, const int imm)

VDBPSADBW zmm {k}, zmm, zmm, imm8 EVEX.512 -mavx512bw

_mm512_maskz_dbsad_epu8 __m512i _mm512_maskz_dbsad_epu8(__mmask32 U, __m512i A, __m512i B, const int imm)

VDBPSADBW zmm {k}{z}, zmm, zmm, imm8 EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512BW_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.