VDBPSADBW

VDBPSADBW computes sums of absolute differences of four unsigned bytes, four sums per quadword, each in a word. It works in two steps, in each 128-bit lane:

1. The second source is shuffled: imm8 picks, two bits per position, which of the lane’s four doublewords goes where, as PSHUFD does.
2. In each quadword, the low doubleword of the first source is compared with the shuffled bytes at offsets 0 to 3 and 1 to 4, giving words 0 and 1, and the high doubleword with the bytes at offsets 2 to 5 and 3 to 6, giving words 2 and 3.

A sum is at most 1020, so nothing saturates: in the cases recorded on Zen 5, bytes of FFh against zeros gave 03FCh in every word, and 80h against 7Fh gave 4.

MPSADBW in every lane#

The shuffle makes it more general than MPSADBW, which compares one block with eight windows that each start a byte further on. VDBPSADBW does the same for every lane when the block is in all four doublewords of the first source and imm8 is 94h: the shuffle then lines up the lane’s doublewords 0, 1, 1 and 2, so that the eight words are the SADs at offsets 0 to 7. A ZMM register thus holds 32 such sums, against MPSADBW’s eight; VMPSADBW gets to 16 with AVX2 and to 32 only with AVX10.2. Other immediates give other offsets, and different doublewords in the first source compare two blocks at once.

Masking#

Unlike VPSADBW, it takes a write mask, one bit per word, with merging or zeroing. The mask covers the destination only: a memory source is read in full whatever the mask, and a page fault on it is not suppressed for masked-off words: its exception class, E4NF, is one of those the SDM lists without fault suppression.

It is part of AVX512BW, so -march=x86-64-v4 enables it, and AVX10.1. A C loop of eight sliding 4-byte SADs does not become VDBPSADBW in GCC 14 or Clang 23 at -O2 with that target; the intrinsics _mm512_dbsad_epu8 and kin give it in both, with _mask_ and _maskz_ variants for the two kinds of masking.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

t = 0                            # src3, its doublewords
for i in range(VL // 32):        # shuffled in each lane
    c = imm8 >> 2 * (i % 4) & 3
    t |= src3.d[i - i % 4 + c] << 32 * i
for i in range(VL // 16):        # word i, of quadword i // 4:
    a = 8 * (i // 4) + 4 * (i % 4 // 2)  # 4 bytes of zmm2
    b = 8 * (i // 4) + i % 4             # and of t
    if k1[i]:                    # 1 without a write mask
        s = 0
        for j in range(4):
            x = t >> 8 * (b + j) & 0xFF
            s += abs(zmm2.b[a + j] - x)
        zmm1.w[i] = s
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# src3 is read whatever the mask: a fault in it is not suppressed
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VDBPSADBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTTPS2QQ
• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH

All 686 AVX10.1 instructions