VDIVPD

VDIVPD divides doubles, two, four or eight at a time, and is DIVPD in VEX and EVEX encodings. VDIVPS covers what the encodings add and how compilers trade a division of singles for an estimate; doubles are a different story.

No shortcut for doubles#

With -ffast-math, GCC 14 and Clang 23 at -O2 replace a division of floats by a reciprocal estimate and a Newton-Raphson step, but for a[i] = b[i] / c[i] over doubles they keep VDIVPD: on ymm registers for -march=x86-64-v3, on zmm for znver5, and for -march=x86-64-v4 on zmm in GCC and ymm in Clang. The estimates that exist for doubles, VRCP14PD among them, have a relative error of up to 2^-14, too far from a double’s 53 bits for one refining step. A division by a constant is another matter: see VMULPD.

Zero, infinity and DAZ#

The cases recorded on Zen 5 tell the invalid operation from a division by zero. 0/0 and -0/0 gave the indefinite FFF8000000000000H and set the invalid flag; a finite number over zero gave an infinity of the quotient’s sign and set the divide-by-zero flag; an infinity over zero gave infinity with neither. With DAZ set, a denormal divided by zero counted as 0/0 and gave the indefinite, not an infinity. Under {rd-sae}, the largest denormal divided by -2^-1023 gave its exact quotient, -1.9999999999999996, and no flag changed although MXCSR unmasked the denormal exception.

On Zen 5#

AMD’s Zen 5 guide gives VDIVPD a latency of 13 cycles and a throughput of 0.25 per cycle at every width, against 10 cycles and 0.4 for VDIVPS, in the same divide unit on pipe FP1: a zmm VDIVPD delivers at most two quotients per cycle.

In the optimization guide

What the optimization guide says about VDIVPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Haswell and Broadwell

• AVX2 and FMA: Apart from division, square root, AES and the SSE4.2 string compares, the vector units are 256 bits wide. sources differ

Skylake to Cooper Lake

• Vectors on all parts: Division and square root are pipelined, and 256-bit forms have the latency of 128-bit ones: LLVM’s models give DIVPS 11 cycles, SQRTPS 12, DIVPD 14 and SQRTPD 18.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = zmm2.f64[i]
        b = src3.f64[i]
        zmm1.f64[i] = div(a, b)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VDIVPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VCMPSD
• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS
• VMAXPD
• VMAXPS

All 253 AVX instructions

More AVX10.1 instructions

• VCVTTPS2UDQ
• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH

All 686 AVX10.1 instructions