VDIVPH

VDIVPH divides the halves of its first source by those of the second, element by element, 32 per zmm register, and rounds each quotient correctly under MXCSR.RC, or under {er} on the 512-bit register form. It is VDIVPS for half precision, opcode 5Eh in EVEX map 5, and reports invalid, divide by zero, overflow, underflow, precision and denormal. VADDPH covers the format, the CPUID bits and the encoding; VDIVSH divides the low element only.

Division or reciprocal#

Division is the slow one among the FP16 operations: Intel’s optimization manual gives it about 24 cycles of latency at 512 bits, one every 16 cycles. For halves, the reciprocal estimate of VRCPPH is close enough to need no Newton-Raphson step, and the manual shows that a VRCPPH followed by VMULPH is about three times faster than VDIVPH, with 98% of quotients within 0.5625 ULP when both operands lie in the middle of the range and none worse than about 1.5 ULP, failing only for divisors near the denormals or the largest exponents (Section 18.5.8.2). The two give different results, so a compiler may substitute one for the other only when told it may.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 vectorize c[i] = a[i] / b[i] over global _Float16 arrays to VDIVPH, GCC on zmm and Clang on ymm registers, as well as 1 / a[i] and a[i] / 3. With -ffast-math both switch: the quotient becomes VRCPPH and VMULPH, the reciprocal VRCPPH alone, and the division by 3 a multiplication by the rounded constant 1/3. With that option the scalar x / y stays VDIVSH in GCC and becomes VRCPSH and VMULSH in Clang.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VDIVPH.

In the optimization guide

What the optimization guide says about VDIVPH, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: AVX-512 FP16 adds and multiplies 32 half-precision values per 512-bit register with a latency of four cycles; division and square root take about 31. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm2.f16[i]
        b = src3.f16[i]
        zmm1.f16[i] = div(a, b)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VDIVPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTTPS2UQQ
• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH

All 686 AVX10.1 instructions