VDIVPS

VDIVPS is DIVPS in VEX and EVEX encodings. The DIVPS page covers division by zero against the invalid 0/0, the history of its speed and why compilers replace it; the VEX forms add a separate destination and 256 bits, and the EVEX forms 512 bits, masking, a broadcast single and a rounding mode given in the instruction. On Zen 5, 1 divided by 1.5 times 2^-24 gave 11184811 under MXCSR’s round to nearest and 11184810 under {rz-sae}, which also leaves MXCSR’s flags alone.

Approximations by target#

Without -ffast-math, GCC 14 and Clang 23 at -O2 keep a[i] = b[i] / c[i] a division: VDIVPS on ymm registers for -march=x86-64-v3, on zmm for znver5, and with -march=x86-64-v4 on zmm in GCC and ymm in Clang. With -ffast-math both turn it into an estimate of 1/c[i] and a Newton-Raphson step, but in different ways:

• GCC refines the reciprocal first, as 2r - r * r * c, with VMULPS, VADDPS and VSUBPS, then multiplies by b[i]; it uses no FMA even where the target has it.
• Clang multiplies the estimate by b[i] first and corrects that quotient with VFMSUB213PS and VFNMADD213PS.

The estimate is VRCPPS on ymm registers, which is why Clang uses it for x86-64-v4 too, and VRCP14PS on zmm registers: GCC for x86-64-v4 and both for znver5. Intel’s manual bounds their relative error by 1.5 times 2^-12 and by 2^-14, so even after the Newton-Raphson step the quotients are approximate and can differ from VDIVPS’s correctly rounded ones in the last bits.

On Zen 5#

AMD’s Zen 5 guide lists VDIVPS with a latency of 10 cycles and a throughput of 0.4 per cycle for xmm, ymm and zmm registers alike, so a zmm division delivers four times the quotients of an xmm one in the same time. Its one divide unit also runs every square root (Section 2.11.1), so VSQRTPS competes with VDIVPS for it.

In the optimization guide

What the optimization guide says about VDIVPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Haswell and Broadwell

• AVX2 and FMA: Apart from division, square root, AES and the SSE4.2 string compares, the vector units are 256 bits wide. sources differ

Skylake to Cooper Lake

• Vectors on all parts: Division and square root are pipelined, and 256-bit forms have the latency of 128-bit ones: LLVM’s models give DIVPS 11 cycles, SQRTPS 12, DIVPD 14 and SQRTPD 18.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm2.f32[i]
        b = src3.f32[i]
        zmm1.f32[i] = div(a, b)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VDIVPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VCMPSS
• VCOMISD
• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS
• VMAXPD
• VMAXPS
• VMAXSD

All 253 AVX instructions

More AVX10.1 instructions

• VCVTTSD2SI
• VCVTTSD2USI
• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD

All 686 AVX10.1 instructions