x86-64.net

Instruction

VDIVSD

Divides the low doubles; the other elements come from the first source.

Extensions
Forms
4 (2 VEX, 2 EVEX)
Data
Intel XED v2026.08.23

VDIVSD is DIVSD in VEX and EVEX encodings: the low double of its first source divided by that of its last operand, with the high double copied from the first source and the bits above 127 cleared. VDIVSS shows the reciprocal without a copy, and VADDSS what else the encodings change. The VEX form needs AVX, the EVEX form AVX-512F or AVX10.1.

Still no estimate

The DIVSD page notes that SSE2 has no reciprocal estimate for doubles. AVX-512 has one, VRCP14SD, with a relative error of at most 2^-14, but in our builds GCC 14 and Clang 23 at -O2 do not use it for 1.0 / x or a / b over doubles: with -march=x86-64-v4, -ffast-math and -mrecip, both still emit VDIVSD. Fourteen bits would need two Newton-Raphson steps to reach double precision.

On Zen 5

  • vdivsd xmm4, xmm4, qword ptr [mem], under MXCSR 7F80H (DAZ clear), divided the largest denormal by the smallest normal double and gave exactly 1 - 2^-52 (3FEFFFFFFFFFFFFEH), setting only DE.
  • The EVEX vdivsd xmm1{k4}, xmm2, xmm3, {rz-sae}, with bit 0 of K4 set, divided -0 by +0 while MXCSR (6600H) left the invalid exception unmasked. It returned the indefinite FFF8000000000000H, with no #XM and no IE.
  • Without {sae}, vdivsd xmm14{k2}{z}, xmm8, qword ptr [mem] took +0 / +0 under FFC0H, returned the indefinite and set IE.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows 13 cycles and 0.25 per cycle on pipe FP1, against 10 cycles and 0.4 for VDIVSS.

Forms

Every encoding of VDIVSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VDIVSD xmm, xmm, m64 VDIVSD_XMMdq_XMMdq_MEMqVEX.LIG.F2.0F.WIG 5E /rAVX
VDIVSD xmm, xmm, xmm VDIVSD_XMMdq_XMMdq_XMMqVEX.LIG.F2.0F.WIG 5E /rAVX
VDIVSD xmm {k}{z}, xmm, xmm, {er} VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512EVEX.LIG.F2.0F.W1 5E /rAVX10.1 or AVX512F
VDIVSD xmm {k}{z}, xmm, m64 VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512EVEX.LIG.F2.0F.W1 5E /rAVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m64
xmm {k}{z}, xmm, m64		xmm, xmm, xmm
xmm {k}{z}, xmm, xmm, {er}
Sandy Bridge28 / 22SBFPDivider p022 / 22SBFPDivider p0
Haswell25 / 14HWFPDivider p020 / 14HWFPDivider p0
Broadwell19 / 8BWFPDivider p014 / 4BWFPDivider p0
Skylake19 / 4SKLFPDivider p014 / 4SKLFPDivider p0
Skylake-SP19 / 4SKXFPDivider p014 / 4SKXFPDivider p0
Ice Lake19 / 4ICXFPDivider p014 / 4ICXFPDivider p0
Alder Lake, Sapphire Rapids20 / 1p014 / 1p0
Lunar Lake20 / 0.5V2 V310 / 5V0 V1
Piledriver14 / 4.5FPFMA FPU19 / 4.5FPFMA FPU1
Zen20 / 5FPU313 / 5FPU3
Zen 220 / 6FPU313 / 6FPU3
Zen 3, Zen 420 / 5FP113 / 5FP1
Jaguar24 / 19FPM FPU119 / 19FPM FPU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low double is computed; the other double comes from xmm2.
VDIVSD: the low elementResult double 0 is computed from double 0 of xmm2 and xmm3; double 1 is that of xmm2. Result doubles 1 to 0: a1, a0/b0.01xmm2a1k1a0/b0a1xmm101xmm3or m64b

The write mask k1 applies to the low double: with bit 0 clear it keeps its old value, or is zeroed with {z}.

Result double 0 is computed from double 0 of xmm2 and xmm3; double 1 is that of xmm2. Result doubles 1 to 0: a1, a0/b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    a = xmm2.f64[0]
    b = src3.f64[0]
    xmm1.f64[0] = div(a, b)
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VDIVSD xmm, xmm, xmm/m64
xmmexplicitwrite
xmmexplicitread
xmm/m64explicitread
VDIVSD xmm {k}{z}, xmm, xmm/m64, {er}
xmmexplicitwrite (masked)
{k}explicitread (write mask)
xmmexplicitread
xmm/m64explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-3
EVEX forms
AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms
follows MXCSR
EVEX forms
write masking
EVEX memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VDIVSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_div_round_sd __m128d _mm_div_round_sd(__m128d A, __m128d B, const int R)

VDIVSD xmm, xmm, xmm, {er} EVEX.LIG -mavx512f

_mm_div_sd __m128d _mm_div_sd(__m128d __a, __m128d __b)

VDIVSD xmm, xmm, xmm VEX.LIG -mavxwith AVX enabled

_mm_mask_div_round_sd __m128d _mm_mask_div_round_sd(__m128d W, __mmask8 U, __m128d A, __m128d B, const int R)

VDIVSD xmm {k}, xmm, xmm, {er} EVEX.LIG -mavx512f

_mm_mask_div_sd __m128d _mm_mask_div_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B)

VDIVSD xmm {k}, xmm, xmm EVEX.LIG -mavx512f

_mm_maskz_div_round_sd __m128d _mm_maskz_div_round_sd(__mmask8 U, __m128d A, __m128d B, const int R)

VDIVSD xmm {k}{z}, xmm, xmm, {er} EVEX.LIG -mavx512f

_mm_maskz_div_sd __m128d _mm_maskz_div_sd(__mmask8 __U, __m128d __A, __m128d __B)

VDIVSD xmm {k}{z}, xmm, xmm EVEX.LIG -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_SCALAR

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-273 (DIVSD)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.