VDIVSH

VDIVSH divides the low half of its first source by the low half of the second and rounds the quotient correctly, under MXCSR.RC or a rounding mode given in the instruction ({er}, register forms only). Bits 127:16 come from the first source and the bits above 127 are cleared, as VDIVSS does for singles. It is the scalar form of VDIVPH, whose page compares division with the reciprocal estimate, and is opcode 5Eh with the F3 prefix in EVEX map 5. Being EVEX-only, it takes a write mask on the one element and xmm16 to xmm31, and reads two bytes when its second source is in memory. It reports invalid, divide by zero, overflow, underflow, precision and denormal. VADDPH covers the format, the CPUID bits and FP16’s use of MXCSR; VMULSH multiplies.

Where compilers use it#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile x / y on _Float16 values to one vdivsh xmm0, xmm0, xmm1, and x / 3 to VDIVSH with the constant read from memory. A division by 4 becomes a VMULSH by 0.25 in both, since the reciprocal of a power of two is exact. Both also compile (_Float16)((float)x / (float)y), a quotient of singles narrowed to a half, to a single VDIVSH; kept as a float, the same quotient is two VCVTSH2SS and a VDIVSS.

-ffast-math splits them. GCC keeps VDIVSH for x / y and 1 / x, and only turns x / 3 into a multiplication by the rounded 1/3. Clang also replaces the variable divisor: x / y becomes VRCPSH and VMULSH, and 1 / x VRCPSH alone. Intel’s optimization manual finds the estimate within 0.5625 ULP of the true reciprocal for all valid inputs (Section 18.5.8.1), so these results can differ from VDIVSH’s in the last bit, and the quotient more for divisors near the ends of the range (Section 18.5.8.2).

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VDIVSH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm2.f16[0]
    b = src3.f16[0]
    xmm1.f16[0] = div(a, b)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VDIVSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTTSH2SI
• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD

All 686 AVX10.1 instructions