VDIVSS

VDIVSS is DIVSS in VEX and EVEX encodings: the low single of its first source divided by that of its last operand, with singles 1 to 3 copied from the first source and the bits above 127 cleared. The DIVSS page shows which divisions compilers turn into multiplications, and VADDSS what the encodings change. The VEX form needs AVX, the EVEX form AVX-512F or AVX10.1.

Reciprocals#

1.0f / x needs the 1 as the dividend. DIVSS overwrites its dividend, so the baseline build adds a MOVAPS; in our builds with -march=x86-64-v3 or x86-64-v4, GCC 14 and Clang 23 at -O2 load the 1 with VMOVSS and write vdivss xmm0, xmm1, xmm0. -ffast-math keeps that division at both levels. Only -mrecip as well replaces it, by the estimate VRCPSS and a Newton-Raphson step, never by AVX-512’s VRCP14SS, even for x86-64-v4.

Denormals on Zen 5#

DIVSS’s page divides the largest denormal by the denormal -2^-127 with DAZ set and gets the indefinite NaN, since both inputs count as zeros. With MXCSR at 7F80H (round toward zero, DAZ clear), vdivss xmm1, xmm2, dword ptr [mem] divided the same two numbers and gave -1.99999976 (BFFFFFFEH), the exact quotient, setting only DE.

Two more recorded cases:

• vdivss xmm12, xmm6, xmm6, under 3FC0H, divided the signaling NaN FF800001H by itself, gave FFC00001H and set IE.
• vdivss xmm14{k4}{z}, xmm8, dword ptr [mem], with bit 0 of K4 set, divided 1 by -2^-24 and gave -16777216, exactly -2^24.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows 10 cycles and 0.4 per cycle on pipe FP1, like DIVSS. VDIVSD is the double form.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    a = xmm2.f32[0]
    b = src3.f32[0]
    xmm1.f32[0] = div(a, b)
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VDIVSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VCOMISS
• VCVTDQ2PD
• VCVTDQ2PS
• VCVTPD2DQ
• VCVTPD2PS
• VCVTPS2DQ
• VCVTPS2PD
• VCVTSD2SI
• VCVTSD2SS
• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS
• VMAXPD
• VMAXPS
• VMAXSD
• VMAXSS
• VMINPD

All 253 AVX instructions

More AVX10.1 instructions

• VCVTTSH2USI
• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS

All 686 AVX10.1 instructions