Instruction
VDPBF16PS
Multiplies pairs of bfloat16 values and adds both products to the matching single-precision accumulator.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VDPBF16PS xmm {k}{z}, xmm, xmm
VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512 | EVEX.128.F3.0F38.W0 52 /r | AVX10.1 or AVX512_BF16 |
VDPBF16PS xmm {k}{z}, xmm, m128/m32bcst
VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512 | EVEX.128.F3.0F38.W0 52 /r | AVX10.1 or AVX512_BF16 |
VDPBF16PS ymm {k}{z}, ymm, ymm
VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512 | EVEX.256.F3.0F38.W0 52 /r | AVX10.1 or AVX512_BF16 |
VDPBF16PS ymm {k}{z}, ymm, m256/m32bcst
VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512 | EVEX.256.F3.0F38.W0 52 /r | AVX10.1 or AVX512_BF16 |
VDPBF16PS zmm {k}{z}, zmm, zmm
VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512 | EVEX.512.F3.0F38.W0 52 /r | AVX10.1 or AVX512_BF16 |
VDPBF16PS zmm {k}{z}, zmm, m512/m32bcst
VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512 | EVEX.512.F3.0F38.W0 52 /r | AVX10.1 or AVX512_BF16 |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VDPBF16PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_dpbf16_ps
__m128 _mm_dpbf16_ps(__m128 __D, __m128bh __A, __m128bh __B) |
|
_mm_mask_dpbf16_ps
__m128 _mm_mask_dpbf16_ps(__m128 __D, __mmask8 __U, __m128bh __A, __m128bh __B) |
|
_mm_maskz_dpbf16_ps
__m128 _mm_maskz_dpbf16_ps(__mmask8 __U, __m128 __D, __m128bh __A, __m128bh __B) |
|
_mm256_dpbf16_ps
__m256 _mm256_dpbf16_ps(__m256 __D, __m256bh __A, __m256bh __B) |
|
_mm256_mask_dpbf16_ps
__m256 _mm256_mask_dpbf16_ps(__m256 __D, __mmask8 __U, __m256bh __A, __m256bh __B) |
|
_mm256_maskz_dpbf16_ps
__m256 _mm256_maskz_dpbf16_ps(__mmask8 __U, __m256 __D, __m256bh __A, __m256bh __B) |
|
_mm512_dpbf16_ps
__m512 _mm512_dpbf16_ps(__m512 __D, __m512bh __A, __m512bh __B) |
|
_mm512_mask_dpbf16_ps
__m512 _mm512_mask_dpbf16_ps(__m512 __D, __mmask16 __U, __m512bh __A, __m512bh __B) |
|
_mm512_maskz_dpbf16_ps
__m512 _mm512_maskz_dpbf16_ps(__mmask16 __U, __m512 __D, __m512bh __A, __m512bh __B) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512_BF16_128 | AVX10.1 or AVX512_BF16 | Nova Lake, Cooper Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
AVX512_BF16_256 | AVX10.1 or AVX512_BF16 | Nova Lake, Cooper Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
AVX512_BF16_512 | AVX10.1 or AVX512_BF16 | Nova Lake, Cooper Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AVX10.1 instructions
- VCVTTSS2SI
- VCVTTSS2USI
- VCVTUDQ2PD
- VCVTUDQ2PH
- VCVTUDQ2PS
- VCVTUQQ2PD
- VCVTUQQ2PH
- VCVTUQQ2PS
- VCVTUSI2SD
- VCVTUSI2SH
- VCVTUSI2SS
- VCVTUW2PH
- VCVTW2PH
- VDBPSADBW
- VDIVPD
- VDIVPH
- VDIVPS
- VDIVSD
- VDIVSH
- VDIVSS
- VEXPANDPD
- VEXPANDPS
- VEXTRACTF32X4
- VEXTRACTF32X8
- VEXTRACTF64X2
- VEXTRACTF64X4
- VEXTRACTI32X4
- VEXTRACTI32X8
- VEXTRACTI64X2
- VEXTRACTI64X4
- VEXTRACTPS
- VFCMADDCPH
- VFCMADDCSH
- VFCMULCPH
- VFCMULCSH
- VFIXUPIMMPD
- VFIXUPIMMPS
- VFIXUPIMMSD
- VFIXUPIMMSS
- VFMADD132PD
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.