VDPBF16PS

VDPBF16PS is the dot-product step for bfloat16 data. Each doubleword of the two sources holds a pair of bfloat16 values; the instruction multiplies the pairs element by element and adds both products to the single-precision accumulator in the destination. A bfloat16 value is the upper half of a single, with the same 8-bit exponent and a 7-bit fraction. 16 pairs fit a ZMM register, which keeps 16 sums. Its integer relatives are VPDPWSSD and VPDPBUSD.

Fixed arithmetic, no MXCSR#

The instruction ignores MXCSR and never changes it: it rounds to nearest even, treats denormal inputs as zero, flushes denormal results to zero, and reports no exception, whatever the control bits say. Every recorded case on Zen 5 left MXCSR as it was, including one with every exception unmasked, where an overflow to infinity and -infinity + infinity, which gave a NaN, raised no #XM; and two products of about 7.3e-40 gave 0 with FTZ off.

The two products are added one at a time, each with its own rounding, the upper pair first. Two cases recorded on Zen 5 show it:

• 1.0 + 2^-24 + 2^-24 gave 1.0, not 1 + 2^-23: each addition rounded the half-way result back to 1.0.
• With products of -6.8e38 in the upper pair and +6.8e38 in the lower one, and an accumulator of 0, the result was -infinity: the first sum overflowed before the second was added.

Code that compares its results with a float loop must allow for both, and for the flushed denormals.

Feeding it#

One way to produce the operands is VCVTNE2PS2BF16, which rounds two vectors of singles to bfloat16 and packs them into one register; Intel’s optimization manual uses it the same way to prepare bfloat16 inputs for AMX (Section 20.11.4, Example 20-23). Neither GCC 14 nor Clang 23 at -O2 with -march=znver5, whose Zen 5 target includes AVX512_BF16, turns a C loop over __bf16 arrays into VDPBF16PS, even with -ffast-math: Clang widens the values to floats by shifting them 16 bits left and uses VFMADD231PS, and GCC stays scalar. The intrinsics _mm512_dpbf16_ps and kin give the instruction in both. AMX’s TDPBF16PS does the same work on tiles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        x = zmm1.f32[i]
        a = zmm2.bf16[2 * i + 1]
        b = src3.bf16[2 * i + 1]
        x = fmadd_ne(a, b, x)
        a = zmm2.bf16[2 * i]
        b = src3.bf16[2 * i]
        zmm1.f32[i] = fmadd_ne(a, b, x)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# BF16: to nearest even, denormals flushed, no flags; MXCSR unused
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VDPBF16PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTTSS2SI
• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD

All 686 AVX10.1 instructions