x86-64.net

Instruction

VDPPHPS

Multiplies pairs of half-precision values and adds both products to the matching single-precision accumulator.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VDPPHPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VDPPHPS xmm {k}{z}, xmm, xmm VDPPHPS_XMMf32_MASKmskw_XMM2f16_XMM2f16_AVX512EVEX.128.NP.0F38.W0 52 /rAVX10.2
VDPPHPS xmm {k}{z}, xmm, m128/m32bcst VDPPHPS_XMMf32_MASKmskw_XMM2f16_MEM2f16_AVX512EVEX.128.NP.0F38.W0 52 /rAVX10.2
VDPPHPS ymm {k}{z}, ymm, ymm VDPPHPS_YMMf32_MASKmskw_YMM2f16_YMM2f16_AVX512EVEX.256.NP.0F38.W0 52 /rAVX10.2
VDPPHPS ymm {k}{z}, ymm, m256/m32bcst VDPPHPS_YMMf32_MASKmskw_YMM2f16_MEM2f16_AVX512EVEX.256.NP.0F38.W0 52 /rAVX10.2
VDPPHPS zmm {k}{z}, zmm, zmm VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_ZMM2f16_AVX512EVEX.512.NP.0F38.W0 52 /rAVX10.2
VDPPHPS zmm {k}{z}, zmm, m512/m32bcst VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_MEM2f16_AVX512EVEX.512.NP.0F38.W0 52 /rAVX10.2

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VDPPHPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_dpph_ps __m128 _mm_dpph_ps(__m128 __W, __m128h __A, __m128h __B)

VDPPHPS xmm, xmm, xmm EVEX.128 -mavx10.2

_mm_mask_dpph_ps __m128 _mm_mask_dpph_ps(__m128 __W, __mmask8 __U, __m128h __A, __m128h __B)

VDPPHPS xmm {k}, xmm, xmm EVEX.128 -mavx10.2

_mm_maskz_dpph_ps __m128 _mm_maskz_dpph_ps(__mmask8 __U, __m128 __W, __m128h __A, __m128h __B)

VDPPHPS xmm {k}{z}, xmm, xmm EVEX.128 -mavx10.2

_mm256_dpph_ps __m256 _mm256_dpph_ps(__m256 __W, __m256h __A, __m256h __B)

VDPPHPS ymm, ymm, ymm EVEX.256 -mavx10.2

_mm256_mask_dpph_ps __m256 _mm256_mask_dpph_ps(__m256 __W, __mmask8 __U, __m256h __A, __m256h __B)

VDPPHPS ymm {k}, ymm, ymm EVEX.256 -mavx10.2

_mm256_maskz_dpph_ps __m256 _mm256_maskz_dpph_ps(__mmask8 __U, __m256 __W, __m256h __A, __m256h __B)

VDPPHPS ymm {k}{z}, ymm, ymm EVEX.256 -mavx10.2

_mm512_dpph_ps __m512 _mm512_dpph_ps(__m512 __W, __m512h __A, __m512h __B)

VDPPHPS zmm, zmm, zmm EVEX.512 -mavx10.2

_mm512_mask_dpph_ps __m512 _mm512_mask_dpph_ps(__m512 __W, __mmask16 __U, __m512h __A, __m512h __B)

VDPPHPS zmm {k}, zmm, zmm EVEX.512 -mavx10.2

_mm512_maskz_dpph_ps __m512 _mm512_maskz_dpph_ps(__mmask16 __U, __m512 __W, __m512h __A, __m512h __B)

VDPPHPS zmm {k}{z}, zmm, zmm EVEX.512 -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_VNNI_FP16_128

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX512_VNNI_FP16_256

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX512_VNNI_FP16_512

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.