VDPPHPS

VDPPHPS is the dot-product step for half precision: each doubleword of the two sources holds a pair of FP16 values, and the instruction adds both products of a pair to the single in the same position of the destination, 4, 8 or 16 sums for an xmm, ymm or zmm register. The third source can be a register, memory, or one pair broadcast from memory, and a write mask has one bit per single. It does for FP16 what VDPBF16PS does for bfloat16, in the slot beside it: opcode 52h in map 0F38, W0, with no prefix, where VDPBF16PS has F3 and VPDPWSSD, the integer word version, 66. Only AVX10.2 has it, not the narrower AVX10_V1_AUX bit that reports some of its conversions and integer dot products.

Two roundings, fixed rules#

The products are added one pair at a time, the upper half of the doubleword first, each sum rounded to a single to nearest even. A product of two halves needs at most 22 significant bits and fits a single exactly, so the roundings are those of the sums: adding two products and the accumulator can give a different single from the exact sum rounded once.

MXCSR is neither read nor written, and nothing is flagged or raised. The rules are fixed instead: FP16 inputs are taken as they are, denormals too, while a denormal accumulator counts as zero and a denormal result becomes zero. VDPBF16PS treats its bfloat16 denormals as zeros; the FP16 ones here count. When several inputs are NaNs, AVX10.2’s description returns the first one, quieted, in the order lower pair, upper pair, accumulator.

In our builds#

GCC 14 has no -mavx10.2. In Clang 23 with -mavx10.2, _mm512_dpph_ps(w, a, b) becomes vdpphps zmm0, zmm1, zmm2 with the accumulator w in zmm0. A loop over _Float16 arrays adding both products of each pair to a float accumulator, at -O2 with -march=x86-64-v4 -mavx10.2, does not use it: Clang splits the pairs with VPMOVDW and VPSRLD, widens them with VCVTPH2PSX, and adds the products with VMULPS, VFMADD231PS and VADDPS, which follow MXCSR. This site’s recorded cases include none of VDPPHPS.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        x = zmm1.f32[i]
        a = zmm2.f16[2 * i + 1]
        b = src3.f16[2 * i + 1]
        x = fmadd_ne(a, b, x)
        a = zmm2.f16[2 * i]
        b = src3.f16[2 * i]
        zmm1.f32[i] = fmadd_ne(a, b, x)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# FP16 inputs taken exactly; each sum to nearest even, single denormals flushed, no flags
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; always rounds to nearest even; denormal results flushed to zero

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VDPPHPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCVTPS2IUBS
• VCVTTBF162IBS
• VCVTTBF162IUBS
• VCVTTPD2DQS
• VCVTTPD2QQS
• VCVTTPD2UDQS
• VCVTTPD2UQQS
• VCVTTPH2IBS
• VCVTTPH2IUBS
• VCVTTPS2DQS
• VCVTTPS2IBS
• VCVTTPS2IUBS
• VCVTTPS2QQS
• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS
• VCVTTSD2USIS
• VCVTTSS2SIS
• VCVTTSS2USIS
• VDIVBF16
• VFMADD132BF16
• VFMADD213BF16
• VFMADD231BF16
• VFMSUB132BF16
• VFMSUB213BF16
• VFMSUB231BF16
• VFNMADD132BF16
• VFNMADD213BF16
• VFNMADD231BF16
• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH

All 96 AVX10.2 instructions