VDPPS instruction (AVX)

Forms

Every encoding of VDPPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VDPPS xmm, xmm, m128, imm8` VDPPS_XMMdq_XMMdq_MEMdq_IMMb	`VEX.128.66.0F3A.WIG 40 /r ib`	AVX
`VDPPS xmm, xmm, xmm, imm8` VDPPS_XMMdq_XMMdq_XMMdq_IMMb	`VEX.128.66.0F3A.WIG 40 /r ib`	AVX
`VDPPS ymm, ymm, m256, imm8` VDPPS_YMMqq_YMMqq_MEMqq_IMMb	`VEX.256.66.0F3A.WIG 40 /r ib`	AVX
`VDPPS ymm, ymm, ymm, imm8` VDPPS_YMMqq_YMMqq_YMMqq_IMMb	`VEX.256.66.0F3A.WIG 40 /r ib`	AVX

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Dot product: the products of the singles that imm8[7:4] selects are summed, and the sum goes to the singles that imm8[3:0] selects; the others are 0.

Example: imm8 = 0x71 (0111 0001 in binary). Under each element: its bit of imm8[7:4], then of imm8[3:0]. The ymm form repeats this in each 128-bit lane, with the same imm8.

With imm8 = 0x71, result singles 3 to 0: 0, 0, 0, sum.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

zero = to_f32(0)
for l in range(0, VL // 32, 4):  # each 128-bit lane
    if imm8 >> 4 & 1:
        p0 = mul(ymm2.f32[l], src3.f32[l])
    else:
        p0 = zero
    if imm8 >> 5 & 1:
        a = ymm2.f32[l + 1]
        b = src3.f32[l + 1]
        p1 = mul(a, b)
    else:
        p1 = zero
    if imm8 >> 6 & 1:
        a = ymm2.f32[l + 2]
        b = src3.f32[l + 2]
        p2 = mul(a, b)
    else:
        p2 = zero
    if imm8 >> 7 & 1:
        a = ymm2.f32[l + 3]
        b = src3.f32[l + 3]
        p3 = mul(a, b)
    else:
        p3 = zero
    x = add(add(p0, p1), add(p2, p3))
    for i in range(l, l + 4):
        if imm8 >> i - l & 1:
            ymm1.f32[i] = x
        else:
            ymm1.f32[i] = zero
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 40 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VDPPS xmm, xmm, xmm/m128, imm8` `VDPPS ymm, ymm, ymm/m256, imm8`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm/m128, ymm/m256`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-2D

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VDPPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_dp_ps` `__m128 _mm_dp_ps(__m128 X, __m128 Y, const int M)`	`VDPPS xmm, xmm, xmm, imm8` VEX.128 -mavxwith AVX enabled
`_mm256_dp_ps` `__m256 _mm256_dp_ps(__m256 V1, __m256 V2, const int M)`	`VDPPS ymm, ymm, ymm, imm8` VEX.256 -mavx

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions