VERW instruction (System)

Forms

Every encoding of VERW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VERW m16` VERW_MEMw	`0F 00 /5`	Base instruction set
`VERW r16` VERW_GPR16	`0F 00 /5`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

sel = src.read()                 # a selector, 16 bits
ok = 0
if sel & 0xFFFC and in_table(sel):
    d = descriptor(sel)          # not null, and within its table
    dpl = d >> 45 & 3
    if d >> 44 & 1 and d >> 40 & 0xA == 2:
        ok = CPL <= dpl and sel & 3 <= dpl
                                 # writable data, visible from CPL
                                 # and RPL; code never passes
zf = ok                          # neither manual names P among the
                                 # checks

Run on AMD Zen 5 (EPYC 9645): 19 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VERW r/m16`
`r/m16`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified; blank: not affected. How to read.

ZF
All forms
M

Attributes

What else XED records about the forms. How to read.

All forms: not in real-address mode

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I286PROTECTED` System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

VERW