x86-64.net

Instruction

VEXPANDPD

Spreads consecutive doubles from the low end of a register or from memory to the positions selected by a mask.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VEXPANDPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VEXPANDPD zmm {k}{z}, m512 VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512EVEX.512.66.0F38.W1 88 /rAVX10.1 or AVX512F
VEXPANDPD zmm {k}{z}, zmm VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512EVEX.512.66.0F38.W1 88 /rAVX10.1 or AVX512F
VEXPANDPD xmm {k}{z}, m128 VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512EVEX.128.66.0F38.W1 88 /rAVX10.1 or AVX512F + AVX512VL
VEXPANDPD xmm {k}{z}, xmm VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512EVEX.128.66.0F38.W1 88 /rAVX10.1 or AVX512F + AVX512VL
VEXPANDPD ymm {k}{z}, m256 VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512EVEX.256.66.0F38.W1 88 /rAVX10.1 or AVX512F + AVX512VL
VEXPANDPD ymm {k}{z}, ymm VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512EVEX.256.66.0F38.W1 88 /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VEXPANDPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_mask_expand_pd __m128d _mm_mask_expand_pd(__m128d __W, __mmask8 __U, __m128d __A)

VEXPANDPD xmm {k}, xmm EVEX.128 -mavx512vl

_mm_mask_expandloadu_pd __m128d _mm_mask_expandloadu_pd(__m128d __W, __mmask8 __U, const void *__P)

VEXPANDPD xmm {k}, m128 EVEX.128 -mavx512vl

_mm_maskz_expand_pd __m128d _mm_maskz_expand_pd(__mmask8 __U, __m128d __A)

VEXPANDPD xmm {k}{z}, xmm EVEX.128 -mavx512vl

_mm_maskz_expandloadu_pd __m128d _mm_maskz_expandloadu_pd(__mmask8 __U, const void *__P)

VEXPANDPD xmm {k}{z}, m128 EVEX.128 -mavx512vl

_mm256_mask_expand_pd __m256d _mm256_mask_expand_pd(__m256d __W, __mmask8 __U, __m256d __A)

VEXPANDPD ymm {k}, ymm EVEX.256 -mavx512vl

_mm256_mask_expandloadu_pd __m256d _mm256_mask_expandloadu_pd(__m256d __W, __mmask8 __U, const void *__P)

VEXPANDPD ymm {k}, m256 EVEX.256 -mavx512vl

_mm256_maskz_expand_pd __m256d _mm256_maskz_expand_pd(__mmask8 __U, __m256d __A)

VEXPANDPD ymm {k}{z}, ymm EVEX.256 -mavx512vl

_mm256_maskz_expandloadu_pd __m256d _mm256_maskz_expandloadu_pd(__mmask8 __U, const void *__P)

VEXPANDPD ymm {k}{z}, m256 EVEX.256 -mavx512vl

_mm512_mask_expand_pd __m512d _mm512_mask_expand_pd(__m512d __W, __mmask8 __U, __m512d __A)

VEXPANDPD zmm {k}, zmm EVEX.512 -mavx512f

_mm512_mask_expandloadu_pd __m512d _mm512_mask_expandloadu_pd(__m512d __W, __mmask8 __U, const void *__P)

VEXPANDPD zmm {k}, m512 EVEX.512 -mavx512f

_mm512_maskz_expand_pd __m512d _mm512_maskz_expand_pd(__mmask8 __U, __m512d __A)

VEXPANDPD zmm {k}{z}, zmm EVEX.512 -mavx512f

_mm512_maskz_expandloadu_pd __m512d _mm512_maskz_expandloadu_pd(__mmask8 __U, const void *__P)

VEXPANDPD zmm {k}{z}, m512 EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.