VEXPANDPD

VEXPANDPD spreads consecutive doubles from the low end of a register, or from memory, over the destination elements whose mask bits are set, in order; the other elements keep their values or, with {z}, become zero. It is VEXPANDPS on 64-bit elements, 2, 4 or 8 of them, and like it does no arithmetic: no SIMD floating-point exception, no MXCSR, NaNs moved bit for bit. It differs from VPEXPANDQ only in the opcode and the intrinsics that produce it. The memory form reads only as many doubles as the mask selects, as VPEXPANDD’s page describes, and VCOMPRESSPD is the reverse.

Recorded on Zen 5#

• Four of eight. With mask bits 0, 3, 6 and 7 set, the first four doubles of a 64-byte buffer landed in elements 0, 3, 6 and 7 of ZMM24, and the other four elements kept their values.
• No element selected. An XMM form whose mask bits 0 and 1 were clear gave zero with {z}, and the register was cleared from bit 128 up, as for every EVEX write.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 emit VEXPANDPD for _mm512_mask_expand_pd and its maskz and expandloadu forms. With the constant mask 0Fh, which keeps the low four elements in place, GCC uses a zeroing masked VMOVAPD and Clang vmovaps ymm0, ymm0; with 55h both keep VEXPANDPD.

AMD’s Zen 5 latency spreadsheet gives two macro-ops on pipes FP1 or FP2 and latencies of 2, 4 and 5 cycles for XMM, YMM and ZMM, as for VEXPANDPS.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

j = 0
for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = src2.q[j]
        j += 1
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VEXPANDPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTTSS2USI
• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH

All 686 AVX10.1 instructions