VEXPANDPS

VEXPANDPS spreads consecutive singles from the low end of a register, or from memory, over the destination elements whose mask bits are set, in order; the other elements keep their values or, with {z}, become zero. It is VPEXPANDD for float data: the same operation on 32-bit elements, with the same encodings apart from the opcode, and that page describes the memory form, which reads only as many elements as the mask selects, and the usual loop around it. VCOMPRESSPS is the reverse.

Bits, not numbers#

Although its name says singles, VEXPANDPS does no arithmetic. It raises no SIMD floating-point exception, ignores MXCSR, and moves NaNs, denormals and negative zeros bit for bit, as a move does. Its operation on this site is therefore written on doublewords. The difference from VPEXPANDD lies only in which instruction a compiler chooses: the intrinsics on __m512 give VEXPANDPS, those on __m512i VPEXPANDD.

What compilers do with it#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 emit it for the intrinsics _mm512_mask_expand_ps, _mm512_maskz_expand_ps and the expandloadu forms, and neither produces it from a C loop that hands out consecutive values to selected positions. With a constant mask they simplify:

• With all bits set, an expansion is a plain copy, and both compilers drop the instruction.
• With only the low eight bits set, the first eight elements stay where they are and the rest become zero, which is a zeroing masked move: GCC emits vmovaps zmm0{k1}{z}, zmm0, and Clang vmovaps ymm0, ymm0, whose VEX encoding clears everything above bit 255.
• Any other constant, such as 5555h, keeps VEXPANDPS with the mask loaded into a mask register.

Recorded on Zen 5#

In the cases recorded on Zen 5, the memory form with merging placed the first doublewords of the buffer, in order, in the selected elements and left the others alone, and an XMM memory form whose mask selected none of the four elements gave zero with {z}.

AMD’s Zen 5 guide lists VEXPANDPS as two macro-ops with a latency of 2, 4 and 5 cycles for XMM, YMM and ZMM, the same as VPEXPANDD.

In the optimization guide

What the optimization guide says about VEXPANDPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Shuffles and lane crossing: VPCOMPRESSD and VPEXPANDD replace shuffle tables, but compressing straight to memory is microcode on Zen 4 and Zen 5.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

j = 0
for i in range(VL // 32):
    if k1[i]:
        zmm1.d[i] = src2.d[j]
        j += 1
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VEXPANDPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTUDQ2PD
• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS

All 686 AVX10.1 instructions