VEXTRACTF128 instruction (AVX)

VEXTRACTF128 copies one 128-bit half of a ymm register, the high one when bit 0 of the immediate is 1, to an xmm register or to 16 bytes of memory. It is VEXTRACTI128 for AVX alone: that page covers reductions, the low half that needs no instruction, and narrowing in order, and notes that Clang uses this form for integer data too. VINSERTF128 goes the other way.

What Zen 5 recorded

vextractf128 xmmword ptr [mem], ymm1, 0x93 stored ymm1’s high half and wrote nothing else: the 16 bytes after it kept their values.
vextractf128 xmm1, ymm2, 0x1F copied the high half and cleared bits 128 to 511 of zmm1.

Both immediates had other bits set, which the instruction ignores.

The end of a sum

A sum of four doubles, the last step of a vectorized loop, is the common use: _mm256_extractf128_pd(x, 1) added to the low half with VADDPD on xmm registers, then the two remaining doubles. GCC 14 and Clang 23 at -O2 with -mavx both start that way and differ in the last shuffle, VUNPCKHPD in GCC and VSHUFPD in Clang, before a scalar VADDSD. The minimum of an array of doubles ends the same way when the compiler may vectorize it (see VMINPD). Storing the high half, _mm_storeu_pd(p, _mm256_extractf128_pd(x, 1)), is one instruction, vextractf128 xmmword ptr [rdi], ymm0, 1.

AMD’s Zen 5 guide gives the register form a latency of 3 cycles on the pipes FP1 and FP2, against 1 for VINSERTF128, and makes the store two macro-ops. A reduction pays that latency once, at the end of the loop.

In the optimization guide

What the optimization guide says about VEXTRACTF128, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen and Zen+

Vectors and floating point: VPERM2F128 is microcoded, three cycles in AMD’s spreadsheet and eight macro-ops in LLVM’s model, while VINSERTF128 and VEXTRACTF128, which move one 128-bit half, take a cycle; moving halves with them beats a full permute. sources differ

Forms

Every encoding of VEXTRACTF128 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VEXTRACTF128 m128, ymm, imm8` VEXTRACTF128_MEMdq_YMMqq_IMMb	`VEX.256.66.0F3A.W0 19 /r ib`	AVX
`VEXTRACTF128 xmm, ymm, imm8` VEXTRACTF128_XMMdq_YMMqq_IMMb	`VEX.256.66.0F3A.W0 19 /r ib`	AVX

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Extract: the 128-bit block of ymm2 that imm8 numbers goes to m128.Memory forms

Example: imm8 = 0x02.

With imm8 = 0x02, result quadwords 1 to 0: a1, a0.

Extract: the 128-bit block of ymm2 that imm8 numbers goes to xmm1.Register forms

Example: imm8 = 0x02.

With imm8 = 0x02, result quadwords 1 to 0: a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

Memory forms

mem.write(ymm2.dq[imm8 & 1])

Run on AMD Zen 5 (EPYC 9645): 1 case.

xmm1.write(ymm2.dq[imm8 & 1])
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VEXTRACTF128 xmm/m128, ymm, imm8`
`xmm/m128`	explicit	write
`ymm`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-6

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VEXTRACTF128, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm256_extractf128_pd` `__m128d _mm256_extractf128_pd(__m256d V, const int M)`	`VEXTRACTF128 xmm, ymm, imm8` VEX.256 -mavx
`_mm256_extractf128_ps` `__m128 _mm256_extractf128_ps(__m256 V, const int M)`	`VEXTRACTF128 xmm, ymm, imm8` VEX.256 -mavx
`_mm256_extractf128_si256` `__m128i _mm256_extractf128_si256(__m256i V, const int M)`	`VEXTRACTF128 xmm, ymm, imm8` VEX.256 -mavx
`_mm256_extractf32x4_ps` `__m128 _mm256_extractf32x4_ps(__m256 A, const int imm)`	`VEXTRACTF128 xmm, ymm, imm8` VEX.256 -mavx512vl
`_mm256_extractf64x2_pd` `__m128d _mm256_extractf64x2_pd(__m256d A, const int imm)`	`VEXTRACTF128 xmm, ymm, imm8` VEX.256 -mavx512vl -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

What Zen 5 recorded#

The end of a sum#