VEXTRACTF32X4

VEXTRACTF32X4 copies one 128-bit block of a YMM or ZMM register to an XMM register or to 16 bytes of memory, under a mask of singles. It does what VEXTRACTI32X4 does, whose page explains the immediate (bits 1:0 at 512 bits, bit 0 at 256), the zeroing of the register form and the merge-only memory form; only the name differs. From a YMM register, unmasked, it matches AVX’s VEXTRACTF128.

Recorded on Zen 5#

The values are moved as bits. In vextractf32x4 xmm1{k5}, zmm2, 0x47 bits 1:0 of 47h chose block 3, and bit 0 of K5 let only its first single through: FFF2E5D8h, a NaN, arrived unchanged, and MXCSR stayed at 1F80h. Singles 1 to 3 of XMM1 kept their values and the bits above 127 were cleared. The memory form vextractf32x4 [mem]{k7}, zmm5, 0x62 stored the first two singles of block 2, by 3h in the low bits of K7, and left the other 8 bytes alone.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile _mm512_extractf32x4_ps and its masked forms to VEXTRACTF32X4, and both store straight from it for _mm_storeu_ps(p, _mm512_extractf32x4_ps(x, 3)). For the 256-bit _mm256_extractf32x4_ps GCC keeps the EVEX instruction where Clang emits VEXTRACTF128. Horizontal sums and maxima end with it in GCC: _mm512_reduce_add_ps and _mm512_reduce_max_ps fold the high 256 bits onto the low with VEXTRACTF64X4, then the high 128 bits of that with VEXTRACTF32X4; Clang uses VEXTRACTF128 for the second step.

AMD’s Zen 5 latency spreadsheet gives it the costs of VEXTRACTI32X4: 3 cycles from a YMM register and 5 from a ZMM register, one more for the memory forms, which take two macro-ops, and two per cycle. The 4 recorded cases cover the register and memory forms at both widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = imm8 & (VL // 128 - 1)  # the 128-bit block
for i in range(4):
    if k1[i]:
        xmm1.d[i] = zmm2.d[x * 4 + i]
    elif zeroing:
        xmm1.d[i] = 0
    # else: xmm1.d[i] keeps its value
# xmm1 is zeroed from bit 128 up

x = imm8 & (VL // 128 - 1)  # the 128-bit block
for i in range(4):
    if k1[i]:
        mem.d[i] = zmm2.d[x * 4 + i]
    # else: mem.d[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E6NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VEXTRACTF32X4, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTUDQ2PH
• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD

All 686 AVX10.1 instructions