VEXTRACTF32X8

VEXTRACTF32X8 copies the low or high 256 bits of a ZMM register, chosen by bit 0 of the immediate, to a YMM register or to 32 bytes of memory, under a mask of singles. It is the floating-point name of VEXTRACTI32X8, whose page covers the forms, and like it needs AVX512DQ (or AVX10.1); unmasked it gives the same result as AVX512F’s VEXTRACTF64X4.

Recorded on Zen 5#

Both recorded cases took the low half, since bit 0 was clear in E2h and C8h. vextractf32x8 ymm0{k2}, zmm31, 0xe2 with C9h in the low byte of K2 wrote singles 0, 3, 6 and 7 of YMM0, kept the other four and cleared bits 256 and up. vextractf32x8 [mem]{k4}, zmm7, 0xc8 with E5h stored singles 0, 2 and 5 to 7 and left the other 12 bytes of the 32 untouched. MXCSR stayed at 1F80h.

In compiled code#

GCC 14 at -O2 with -march=x86-64-v4 and -ffast-math sums a float array in a ZMM register and starts the final reduction with VEXTRACTF32X8 of the high half and an add on YMM registers, then continues with VEXTRACTF32X4. Its _mm512_reduce_add_ps starts with VEXTRACTF64X4 instead, the same bits. _mm512_extractf32x8_ps(x, 1) stays VEXTRACTF32X8 in GCC and becomes VEXTRACTF64X4 in Clang 23, which keeps VEXTRACTF32X8 for the masked form; Clang’s own sum of the array runs in YMM registers and needs no 256-bit extract.

AMD’s Zen 5 latency spreadsheet gives VEXTRACTF32X8 four cycles to a register and five to memory, where it takes two macro-ops, at two per cycle, as VEXTRACTI32X8.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = imm8 & 1  # the 256-bit block
for i in range(8):
    if k1[i]:
        ymm1.d[i] = zmm2.d[x * 8 + i]
    elif zeroing:
        ymm1.d[i] = 0
    # else: ymm1.d[i] keeps its value
# ymm1 is zeroed from bit 256 up

x = imm8 & 1  # the 256-bit block
for i in range(8):
    if k1[i]:
        mem.d[i] = zmm2.d[x * 8 + i]
    # else: mem.d[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E6NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VEXTRACTF32X8, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTUDQ2PS
• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH

All 686 AVX10.1 instructions