VEXTRACTF64X2

VEXTRACTF64X2 copies one 128-bit block of a YMM or ZMM register, two doubles, to an XMM register or to 16 bytes of memory, under a mask of quadwords. It is VEXTRACTI64X2 under a floating-point name, and VEXTRACTI32X4’s page explains the immediate, the zeroing of the register form and the merge-only memory form. VEXTRACTF32X4 does the same with a mask of singles, and from a YMM register, unmasked, the result is that of AVX’s VEXTRACTF128. It came with AVX512DQ.

Recorded on Zen 5#

• Only the low immediate bits. With immediate FBh, the YMM form stored the upper block of YMM5, by bit 0 alone; with 14h, the ZMM form took block 0 of ZMM30, by bits 1:0.
• Nothing selected. vextractf64x2 xmmword ptr [mem]{k6}, zmm7, 19h, with the low two bits of K6 clear, left the 16 bytes of memory as they were; the register form under a zero mask that selected nothing cleared XMM7, and with it the register up to bit 511.

In compiled code#

At -O2 with -march=x86-64-v4 -ffast-math, GCC 14 ends the sum or the maximum of a double array in a ZMM register by halving it: VEXTRACTF64X4, then VEXTRACTF64X2 for the upper half of the YMM result; for floats it uses VEXTRACTF32X8 and VEXTRACTF32X4. Clang 23 accumulates in YMM registers and halves with VEXTRACTF128. The intrinsic _mm512_extractf64x2_pd is VEXTRACTF64X2 in GCC, in register and memory forms, and VEXTRACTF32X4 in Clang; from a YMM register Clang uses VEXTRACTF128.

AMD’s Zen 5 latency spreadsheet gives the register forms one macro-op on pipe FP1 or FP2, with 3 cycles from a YMM and 5 from a ZMM source, and the memory forms a second macro-op.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = imm8 & (VL // 128 - 1)  # the 128-bit block
for i in range(2):
    if k1[i]:
        xmm1.q[i] = zmm2.q[x * 2 + i]
    elif zeroing:
        xmm1.q[i] = 0
    # else: xmm1.q[i] keeps its value
# xmm1 is zeroed from bit 128 up

x = imm8 & (VL // 128 - 1)  # the 128-bit block
for i in range(2):
    if k1[i]:
        mem.q[i] = zmm2.q[x * 2 + i]
    # else: mem.q[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E6NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VEXTRACTF64X2, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTUQQ2PD
• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS

All 686 AVX10.1 instructions