VEXTRACTF64X4

VEXTRACTF64X4 copies the low or high 256 bits of a ZMM register, chosen by bit 0 of the immediate, to a YMM register or to 32 bytes of memory, under a mask of doubles. It is VEXTRACTI64X4 under a floating-point name, with the same bits moved and the same AVX-512F requirement; that page explains the zeroing register form, the merge-only memory form and the reductions that need the high half. Nothing is converted, so no SIMD exception can arise. VEXTRACTF32X8 masks singles instead and needs AVX512DQ, and VINSERTF64X4 is the reverse.

Recorded on Zen 5#

• One register in and out. vextractf64x4 ymm5{k5}, zmm5, 0x81 took the high half, bit 0 of 81h being 1, and with E1h in K5 wrote only double 0 of YMM5, from double 4 of ZMM5; doubles 1 to 3 kept their values, and bits 511:256 were cleared.
• An empty mask stores nothing. vextractf64x4 ymmword ptr [mem]{k1}, zmm7, 0xb with the low four bits of K1 clear left all 32 bytes of memory as they were.

In compiled code#

With GCC 14 and Clang 23 at -O2 and -march=x86-64-v4, _mm512_extractf64x4_pd(x, 1) is VEXTRACTF64X4 in both, and the store of its result one vextractf64x4 ymmword ptr [rdi], zmm0, 1; index 0 needs no instruction, since the low half is the YMM register of the same number. _mm512_reduce_add_pd starts with VEXTRACTF64X4 and a VADDPD of the two halves in both, and so does _mm512_reduce_max_ps for singles, with VMAXPS. Without a mask the element size makes no difference: Clang compiles _mm512_extractf32x8_ps and, as VEXTRACTI64X4’s page shows, the integer extract to VEXTRACTF64X4, while GCC keeps the names of the intrinsics.

AMD’s Zen 5 latency spreadsheet gives VEXTRACTF64X4 one macro-op on pipe FP1 or FP2 and four cycles to a register, and two macro-ops and five cycles to memory, two per cycle, as VEXTRACTI64X4.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = imm8 & 1  # the 256-bit block
for i in range(4):
    if k1[i]:
        ymm1.q[i] = zmm2.q[x * 4 + i]
    elif zeroing:
        ymm1.q[i] = 0
    # else: ymm1.q[i] keeps its value
# ymm1 is zeroed from bit 256 up

x = imm8 & 1  # the 256-bit block
for i in range(4):
    if k1[i]:
        mem.q[i] = zmm2.q[x * 4 + i]
    # else: mem.q[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E6NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VEXTRACTF64X4, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTUQQ2PH
• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD

All 686 AVX10.1 instructions