VEXTRACTI128

VEXTRACTI128 copies one 128-bit half of a YMM register, the high one if bit 0 of the immediate is 1, to an XMM register or to 16 bytes of memory at any alignment. The register form clears the destination’s bits above 127. Its most common use is the end of a vectorized reduction: a loop that sums 32-bit integers in YMM registers is left with eight partial sums, and GCC 14 and Clang 23 at -O2 both fold them by extracting the high half and adding it to the low half in an XMM register, then finish with shifts or shuffles (VPSRLDQ in GCC, VPSHUFD in Clang) and additions. The same pattern serves other horizontal operations, such as a minimum or a maximum.

The low half needs no instruction, since the XMM register is that half of the YMM register: _mm256_extracti128_si256(x, 0) and _mm256_castsi256_si128(x) compile to nothing in either compiler. The memory form stores the high half directly: both compilers turn _mm_storeu_si128(p, _mm256_extracti128_si256(x, 1)) into one instruction (VEXTRACTF128 in Clang).

Narrowing with it#

Instructions that narrow elements, such as VPACKUSWB, work within lanes, so converting 16-bit elements to bytes in order needs either a VPERMQ after a 256-bit pack or a VEXTRACTI128 before a 128-bit one. For a loop that narrows an array of uint16_t to uint8_t, GCC 14 chooses the first and Clang 23 the second. GCC likewise extracts the high half when it widens 32 bytes in order with VPMOVZXBW.

Intel’s optimization guide counts VEXTRACTF128 among the building blocks for code that keeps data in lanes (Section 15.4.1). VEXTRACTF128 is the AVX version, which Clang emits for integer data too when no integer instruction is near. AVX-512 adds VEXTRACTI32X4 and its kin, which take 128 or 256 bits out of ZMM registers and can mask the result. VINSERTI128 is the reverse, and a function that has used YMM registers ends with VZEROUPPER before it returns to code that may run SSE instructions.

In the optimization guide

What the optimization guide says about VEXTRACTI128, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Haswell and Broadwell

• AVX2 and FMA: Every instruction that can move data from one 128-bit half of a YMM register to the other takes 3 cycles, even when it does not: VEXTRACTI128 of the low half still takes 3, where VMOVDQA, which copies the same 128 bits, takes 0 or 1.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

mem.write(ymm2.dq[imm8 & 1])

xmm1.write(ymm2.dq[imm8 & 1])
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-6

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VEXTRACTI128, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VBROADCASTI128
• VBROADCASTSD
• VBROADCASTSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VINSERTI128
• VMOVNTDQA
• VMPSADBW
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ

All 138 AVX2 instructions