VEXTRACTI32X4

VEXTRACTI32X4 copies one 128-bit block of a YMM or ZMM register to an XMM register or to 16 bytes of memory, under a mask of doublewords. In a ZMM register bits 1:0 of the immediate choose among four blocks; in a YMM register bit 0 chooses between two. The other bits are ignored. From a YMM register, unmasked, it does what the AVX2 VEXTRACTI128 does, and that page covers the uses: the end of a reduction, narrowing, storing the high half.

The register form writes the low 128 bits and clears the rest of the destination. The memory form can merge but not zero: masked-out doublewords leave memory untouched. On Zen 5, vextracti32x4 [mem]{k3}, zmm9, 2Fh took block 3 (bits 1:0 of 2Fh) and, with 1011b in the low bits of K3, stored doublewords 0, 1 and 3 of it and left the third doubleword of memory as it was. vextracti32x4 xmm24{k5}{z}, ymm3, 0A9h took the high half of YMM3 and, with 0001b in K5, wrote its first doubleword to XMM24 and zeroed the other three and everything above them in ZMM24.

In compiled code#

GCC 14 at -O2 with -march=x86-64-v4 ends the sum of an int array by folding the zmm accumulator with VEXTRACTI32X8 and an add on ymm registers, then VEXTRACTI32X4 of the high half of that ymm register and an add on xmm registers; a maximum or an XOR ends the same way. Clang 23 sums in ymm registers and needs only VEXTRACTI128.

Both compilers emit VEXTRACTI32X4 under a mask, for _mm512_maskz_extracti32x4_epi32. Unmasked, Clang uses VEXTRACTF32X4, the same bits, and for _mm_storeu_si128(p, _mm512_extracti32x4_epi32(x, 2)) stores straight from the extract; GCC extracts to a register and stores with VMOVDQU. Block 0 needs no instruction in either compiler, since the XMM register is the low block of the ZMM register.

AMD’s Zen 5 latency spreadsheet makes the source width matter: three cycles from a YMM register (as for the VEX VEXTRACTI128) and five from a ZMM register, plus one more for the memory forms, which take two macro-ops; two per cycle throughout. Zen 5’s 4 recorded cases cover the register and memory forms at both widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = imm8 & (VL // 128 - 1)  # the 128-bit block
for i in range(4):
    if k1[i]:
        xmm1.d[i] = zmm2.d[x * 4 + i]
    elif zeroing:
        xmm1.d[i] = 0
    # else: xmm1.d[i] keeps its value
# xmm1 is zeroed from bit 128 up

x = imm8 & (VL // 128 - 1)  # the 128-bit block
for i in range(4):
    if k1[i]:
        mem.d[i] = zmm2.d[x * 4 + i]
    # else: mem.d[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E6NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VEXTRACTI32X4, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTUQQ2PS
• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH

All 686 AVX10.1 instructions