VEXTRACTI32X8

VEXTRACTI32X8 copies the low or high 256 bits of a ZMM register, chosen by bit 0 of the immediate, to a YMM register or to 32 bytes of memory, under a mask of doublewords. It exists only at 512 bits and needs AVX512DQ (or AVX10.1). Unmasked it gives the same result as VEXTRACTI64X4, which needs only AVX512F; the two differ in the element size of the mask, as VEXTRACTI32X4 and VEXTRACTI64X2 do for 128-bit blocks, whose pages cover the register and memory forms.

On Zen 5, vextracti32x8 ymm0{k1}, zmm31, 0B3h took the high half (bit 0 of 0B3h is 1) and, with A0h in the low byte of K1, wrote only doublewords 5 and 7 of YMM0, kept the other six and cleared the bits from 256 up. The memory form, vextracti32x8 [mem]{k2}, zmm0, 91h with C9h in K2, stored doublewords 0, 3, 6 and 7 of the high half and left the rest of the 32 bytes untouched.

In compiled code#

GCC 14 at -O2 with -march=x86-64-v4 begins the end of a reduction over 32-bit elements with it: summing an int array leaves 16 partial sums in a zmm register, and GCC adds VEXTRACTI32X8 of the high half to the low half on ymm registers, then goes on with VEXTRACTI32X4 as that page shows. For 64-bit elements it uses VEXTRACTI64X4 instead, and with -mavx512f, which lacks AVX512DQ, for 32-bit ones too. _mm512_extracti32x8_epi32(x, 1) is VEXTRACTI32X8 in GCC and VEXTRACTF64X4 in Clang 23, which keeps the integer name for masked forms such as _mm512_mask_extracti32x8_epi32.

AMD’s Zen 5 latency spreadsheet gives VEXTRACTI32X8 four cycles to a register and five to memory, where it takes two macro-ops, at two per cycle, the same as VEXTRACTI64X4. Zen 5’s 2 recorded cases cover the register and memory forms.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = imm8 & 1  # the 256-bit block
for i in range(8):
    if k1[i]:
        ymm1.d[i] = zmm2.d[x * 8 + i]
    elif zeroing:
        ymm1.d[i] = 0
    # else: ymm1.d[i] keeps its value
# ymm1 is zeroed from bit 256 up

x = imm8 & 1  # the 256-bit block
for i in range(8):
    if k1[i]:
        mem.d[i] = zmm2.d[x * 8 + i]
    # else: mem.d[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E6NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VEXTRACTI32X8, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTUSI2SD
• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS

All 686 AVX10.1 instructions