VEXTRACTI64X2

VEXTRACTI64X2 is VEXTRACTI32X4 with a mask of quadwords: it copies one 128-bit block of a YMM or ZMM register, chosen by bits 1:0 of the immediate (bit 0 for YMM), to an XMM register or to 16 bytes of memory. It needs AVX512DQ (and AVX512VL for a YMM source), where VEXTRACTI32X4 needs only AVX512F. Unmasked the two give the same result, and the VEXTRACTI32X4 page covers the register and memory forms.

On Zen 5, vextracti64x2 xmm0{k2}, zmm31, 7 took block 3, the top 16 bytes of ZMM31, and with 01b in the low bits of K2 wrote its first quadword and kept the second of XMM0. A fully masked store wrote nothing: vextracti64x2 [mem]{k6}, zmm1, 0BEh with 00b in the low bits of K6 left the 16 bytes as they were.

In compiled code#

GCC 14 at -O2 with -march=x86-64-v4 uses VEXTRACTI64X2 in the last steps of a reduction: after VEXTRACTI64X4 has folded a zmm register to ymm, VEXTRACTI64X2 of the high half of that ymm register folds it to xmm. It does so for the sum or XOR of long long elements in a loop and for _mm512_reduce_add_epi32 and _mm512_reduce_add_epi64. Clang 23 emits VEXTRACTI128 at that step, and with -mavx512f alone, which lacks AVX512DQ and AVX512VL, GCC does too.

Masked, _mm512_mask_extracti64x2_epi64 is VEXTRACTI64X2 in both compilers. Unmasked, Clang extracts block 1 of a zmm register with VEXTRACTF128 of its low ymm half, which needs only AVX.

AMD’s Zen 5 latency spreadsheet gives it the timings of VEXTRACTI32X4: three cycles from a YMM register, five from a ZMM register, one more for the memory forms, two per cycle. Zen 5’s 4 recorded cases cover the register and memory forms at both widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = imm8 & (VL // 128 - 1)  # the 128-bit block
for i in range(2):
    if k1[i]:
        xmm1.q[i] = zmm2.q[x * 2 + i]
    elif zeroing:
        xmm1.q[i] = 0
    # else: xmm1.q[i] keeps its value
# xmm1 is zeroed from bit 128 up

x = imm8 & (VL // 128 - 1)  # the 128-bit block
for i in range(2):
    if k1[i]:
        mem.q[i] = zmm2.q[x * 2 + i]
    # else: mem.q[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E6NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VEXTRACTI64X2, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTUSI2SH
• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD

All 686 AVX10.1 instructions