VEXTRACTI64X4

VEXTRACTI64X4 copies the low or high 256 bits of a ZMM register, chosen by bit 0 of the immediate, to a YMM register or to 32 bytes of memory, under a mask of quadwords. It exists only at 512 bits and needs only AVX512F, so it is the 256-bit extract every AVX-512 processor has; VEXTRACTI32X8 does the same with a mask of doublewords and needs AVX512DQ. It is the reverse of VINSERTI64X4. The register form clears the destination from bit 256 up; the memory form cannot zero, so masked-out quadwords leave memory untouched.

On Zen 5, vextracti64x4 ymm0{k3}, zmm31, 26h took the low half (bit 0 of 26h is 0) and, with 1011b in the low bits of K3, wrote quadwords 0, 1 and 3 and kept quadword 2 of YMM0. The low half of a ZMM register is the YMM register of the same number, so an extract of it is only needed for a mask or for another destination.

Halving a vector#

The high half is what reductions need. GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile _mm512_reduce_add_epi32 and _mm512_reduce_max_epi32 to VEXTRACTI64X4 and an operation on the two halves, then a 128-bit extract and shuffles: GCC continues with VEXTRACTI64X2, Clang with VEXTRACTI128. In a vectorized loop over long long elements GCC folds its accumulator the same way; over int elements it uses VEXTRACTI32X8, except with -mavx512f, where VEXTRACTI64X4 is the only one available.

For _mm512_extracti64x4_epi64(x, 1) GCC emits VEXTRACTI64X4 and Clang VEXTRACTF64X4, the same bits, and both store the high half with one instruction when the result goes to memory.

AMD’s Zen 5 latency spreadsheet gives VEXTRACTI64X4 four cycles to a register and five to memory, where it takes two macro-ops, at two per cycle. Zen 5’s 2 recorded cases cover the register and memory forms.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = imm8 & 1  # the 256-bit block
for i in range(4):
    if k1[i]:
        ymm1.q[i] = zmm2.q[x * 4 + i]
    elif zeroing:
        ymm1.q[i] = 0
    # else: ymm1.q[i] keeps its value
# ymm1 is zeroed from bit 256 up

x = imm8 & 1  # the 256-bit block
for i in range(4):
    if k1[i]:
        mem.q[i] = zmm2.q[x * 4 + i]
    # else: mem.q[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E6NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VEXTRACTI64X4, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTUSI2SS
• VCVTUW2PH
• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH

All 686 AVX10.1 instructions