x86-64.net

Instruction

VEXTRACTPS

Copies the single that an immediate selects from an XMM register to a general-purpose register or memory.

Extensions
Forms
4 (2 VEX, 2 EVEX)
Data
Intel XED v2026.08.23

VEXTRACTPS is the VEX and EVEX form of EXTRACTPS: it copies the single that bits 1:0 of the immediate pick, as bits, to four bytes of memory or to a 32-bit general-purpose register. EXTRACTPS’s page covers why the register form gives a bit pattern rather than a number and when compilers store with it. Unlike most VEX forms, this one has nothing to add on the destination side: there is no third operand (VEX.vvvv and EVEX.vvvv must be 1111b), no vector register is written, and Intel’s entry raises #UD for VEX.L = 1. The EVEX form, with AVX-512F or AVX10.1, can read XMM16 to XMM31 and has no mask. With W1 and a register destination, Intel’s entry zero-extends the single to 64 bits, which a 32-bit register write does anyway.

Recorded on Zen 5

  • vextractps eax, xmm1, 3Eh copied element 2 into EAX and cleared bits 63:32 of RAX; the immediate’s bits above 1:0 were ignored.
  • vextractps dword ptr [mem], xmm7, 63h stored element 3 and left the bytes after it unchanged.
  • {evex} vextractps dword ptr [mem], xmm17, 18h stored element 0 of a register only EVEX can name.

The upper lane in compiled code

The instruction reads only an XMM register. In our builds at -O2, *p = v[6] on a vector of eight floats needs the upper half first: with -march=x86-64-v3 both GCC 14 and Clang 23 take it with VEXTRACTF128 and store with vextractps dword ptr [rdi], xmm0, 2. With -march=x86-64-v4 Clang does the same (with VEXTRACTI128), while GCC rotates the element into place with VALIGND and stores it with VMOVSS. For the four elements of an XMM register stored to four places, both use a VMOVSS (Clang at -v4 a VMOVD) and three VEXTRACTPS.

AMD’s latency spreadsheet for Zen 5 lists the VEX and EVEX rows as two macro-ops on pipes FP0-3 and FP4/5, the same as EXTRACTPS; it gives a latency of 2 cycles only in the EVEX row.

Forms

Every encoding of VEXTRACTPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VEXTRACTPS m32, xmm, imm8 VEXTRACTPS_MEMd_XMMdq_IMMbVEX.128.66.0F3A.WIG 17 /r ibAVX
VEXTRACTPS r32, xmm, imm8 VEXTRACTPS_GPR32_XMMdq_IMMbVEX.128.66.0F3A.WIG 17 /r ibAVX
VEXTRACTPS r32, xmm, imm8 VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512EVEX.128.66.0F3A.WIG 17 /r ibAVX10.1 or AVX512F
VEXTRACTPS m32, xmm, imm8 VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512EVEX.128.66.0F3A.WIG 17 /r ibAVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelm32, xmm, imm8r32, xmm, imm8
Sandy Bridge5 / 1p53 / 1p05
Haswell, Broadwell2 / 1p52 / 1p05
Skylake, Skylake-SP, Ice Lake2 / 1p53 / 1p05
Alder Lake, Sapphire Rapids12 / 1p54 / 1p05
Lunar Lake12 / 0.5p1354 / 0.5V2 V3 p1 p3 p5
Piledriver13 / 2FPU112 / 1.5EX0 FPFMA FPU0
Zen5 / 2.5FPU1 FPU22 / 2FPU1 FPU2
Zen 25 / 2FPU1 FPU22 / 2FPU1 FPU2
Zen 3, Zen 42 / 1FP45 FPSt LSU Store1 / 1FP45
Jaguar3 / 1FPU13 / 1ALU0 FPA FPU0

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Extract: single imm8 of xmm2 goes to m32.
VEXTRACTPS with imm8 = 0x02With imm8 = 0x02, m32 receives single 2 of xmm2: a2.0132xmm2aa2m32or r32

Example: imm8 = 0x02.

With imm8 = 0x02, m32 receives single 2 of xmm2: a2.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(xmm2.d[imm8 & 3])  # a register: bits 63:32 cleared

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VEXTRACTPS r/m32, xmm, imm8
r/m32explicitwrite
xmmexplicitread
imm8explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-5
EVEX forms
AVX512-E9NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VEXTRACTPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_extract_ps int _mm_extract_ps(__m128 X, const int N)

VEXTRACTPS r32, xmm, imm8 VEX.128 -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_128N

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-305 (EXTRACTPS)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.