VFCMADDCPH

VFCMADDCPH multiplies each complex number of its first source by the complex conjugate of the matching one in the second and adds the product to the destination: acc += x × conj(y) for 16 complex values, pairs of halves, per zmm register. For x = a + bi and y = c + di the real part gains ac + bd and the imaginary part bc - ad. It is VFMADDCPH with the conjugate, F2 instead of F3 on opcode 56h in EVEX map 6, and that page covers the accumulator in the destination and the masked intrinsics; VFCMULCPH explains which operand is conjugated, VFMULCPH the layout, the per-pair masking and the #UD when the destination is a source, and VFCMADDCSH is the scalar form.

Rounding inside#

Like the other complex instructions, VFCMADDCPH is built from fused multiply-adds: for each part Intel’s optimization manual describes two in a row, starting from the accumulator, with a rounding to FP16 after each (Sections 18.4.3 and 18.5.3). The result is therefore not the correctly rounded value of the whole expression. Intel’s entry lists invalid, overflow, underflow, precision and denormal, sets those flags in MXCSR and runs as if all of them were masked.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, z[i] += x[i] * ~y[i] over _Complex _Float16 arrays, ~ being the conjugate in GCC and Clang, stays scalar in both compilers, with a call to the library’s __mulhc3 for a NaN product. With -ffast-math, GCC 14 vectorizes it to VFCMADDCPH on zmm registers with y read from memory; with only -fcx-limited-range it uses VFCMULCPH and a separate VADDPH. Clang 23 uses no complex instruction in these loops and works on separated real and imaginary parts. A correlation that sums x[i] * ~y[i] into a single complex value is not vectorized with VFCMADDCPH by either: GCC builds the products from VMULPH and VFMADDSUB231PH, Clang from real FMAs, and both reduce at the end. The intrinsic _mm512_fcmadd_pch(a, b, c) gives VFCMADDCPH in both, with c as the accumulator.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFCMADDCPH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if zmm1.number == zmm2.number:
    fault(UD)
if not src3.is_memory:
    if zmm1.number == src3.number:
        fault(UD)
for i in range(VL // 32):
    if k1[i]:
        ar = zmm2.f16[2 * i]
        ai = zmm2.f16[2 * i + 1]
        br = src3.f16[2 * i]
        bi = src3.f16[2 * i + 1]
        x = zmm1.f16[2 * i]
        y = zmm1.f16[2 * i + 1]
        x = fmadd(ar, br, x)
        y = fmadd(ai, br, y)
        x = fmadd(ai, bi, x)
        y = fnmadd(ar, bi, y)
        zmm1.d[i] = y << 16 | x
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# x + y*i += (ar + ai*i)(br - bi*i)
# {er}: the form's rounding, not MXCSR.RC, and no flags
# exceptions as if masked (flags, never #XM): the SDM's claim, unchecked here
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFCMADDCPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VCVTW2PH
• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD

All 686 AVX10.1 instructions