x86-64.net

Instruction

VFCMADDCPH

Multiplies packed complex half-precision numbers by the complex conjugates of the second source and adds the products to the destination.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VFCMADDCPH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VFCMADDCPH xmm {k}{z}, xmm, xmm VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512EVEX.128.F2.MAP6.W0 56 /rAVX10.1 or AVX512_FP16 + AVX512VL
VFCMADDCPH xmm {k}{z}, xmm, m128/m32bcst VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512EVEX.128.F2.MAP6.W0 56 /rAVX10.1 or AVX512_FP16 + AVX512VL
VFCMADDCPH ymm {k}{z}, ymm, ymm VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512EVEX.256.F2.MAP6.W0 56 /rAVX10.1 or AVX512_FP16 + AVX512VL
VFCMADDCPH ymm {k}{z}, ymm, m256/m32bcst VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512EVEX.256.F2.MAP6.W0 56 /rAVX10.1 or AVX512_FP16 + AVX512VL
VFCMADDCPH zmm {k}{z}, zmm, zmm, {er} VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512EVEX.512.F2.MAP6.W0 56 /rAVX10.1 or AVX512_FP16
VFCMADDCPH zmm {k}{z}, zmm, m512/m32bcst VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512EVEX.512.F2.MAP6.W0 56 /rAVX10.1 or AVX512_FP16

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFCMADDCPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_fcmadd_pch __m128h _mm_fcmadd_pch(__m128h __A, __m128h __B, __m128h __C)

VFCMADDCPH xmm, xmm, xmm EVEX.128 -mavx512fp16 -mavx512vl

_mm_mask3_fcmadd_pch __m128h _mm_mask3_fcmadd_pch(__m128h __A, __m128h __B, __m128h __C, __mmask8 __U)

VFCMADDCPH xmm {k}, xmm, xmm EVEX.128 -mavx512fp16 -mavx512vl

_mm_maskz_fcmadd_pch __m128h _mm_maskz_fcmadd_pch(__mmask8 __U, __m128h __A, __m128h __B, __m128h __C)

VFCMADDCPH xmm {k}{z}, xmm, xmm EVEX.128 -mavx512fp16 -mavx512vl

_mm256_fcmadd_pch __m256h _mm256_fcmadd_pch(__m256h __A, __m256h __B, __m256h __C)

VFCMADDCPH ymm, ymm, ymm EVEX.256 -mavx512fp16 -mavx512vl

_mm256_mask3_fcmadd_pch __m256h _mm256_mask3_fcmadd_pch(__m256h __A, __m256h __B, __m256h __C, __mmask8 __U)

VFCMADDCPH ymm {k}, ymm, ymm EVEX.256 -mavx512fp16 -mavx512vl

_mm256_maskz_fcmadd_pch __m256h _mm256_maskz_fcmadd_pch(__mmask8 __U, __m256h __A, __m256h __B, __m256h __C)

VFCMADDCPH ymm {k}{z}, ymm, ymm EVEX.256 -mavx512fp16 -mavx512vl

_mm512_fcmadd_pch __m512h _mm512_fcmadd_pch(__m512h __A, __m512h __B, __m512h __C)

VFCMADDCPH zmm, zmm, zmm EVEX.512 -mavx512fp16

_mm512_fcmadd_round_pch __m512h _mm512_fcmadd_round_pch(__m512h A, __m512h B, __m512h C, const int R)

VFCMADDCPH zmm, zmm, zmm, {er} EVEX.512 -mavx512fp16

_mm512_mask3_fcmadd_pch __m512h _mm512_mask3_fcmadd_pch(__m512h __A, __m512h __B, __m512h __C, __mmask16 __U)

VFCMADDCPH zmm {k}, zmm, zmm EVEX.512 -mavx512fp16

_mm512_mask3_fcmadd_round_pch __m512h _mm512_mask3_fcmadd_round_pch(__m512h A, __m512h B, __m512h C, __mmask16 U, const int R)

VFCMADDCPH zmm {k}, zmm, zmm, {er} EVEX.512 -mavx512fp16

_mm512_maskz_fcmadd_pch __m512h _mm512_maskz_fcmadd_pch(__mmask16 __U, __m512h __A, __m512h __B, __m512h __C)

VFCMADDCPH zmm {k}{z}, zmm, zmm EVEX.512 -mavx512fp16

_mm512_maskz_fcmadd_round_pch __m512h _mm512_maskz_fcmadd_round_pch(__mmask16 U, __m512h A, __m512h B, __m512h C, const int R)

VFCMADDCPH zmm {k}{z}, zmm, zmm, {er} EVEX.512 -mavx512fp16

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_FP16_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16 + AVX512VL
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_FP16_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16 + AVX512VL
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_FP16_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.