VFCMADDCSH

VFCMADDCSH multiplies the lowest complex number of its first source by the conjugate of the lowest one in the second and adds the product to the pair in the destination: for x = a + bi and y = c + di the real part gains ac + bd and the imaginary part bc - ad. It is opcode 57h with the F2 prefix in EVEX map 6, the conjugating twin of VFMADDCSH, whose page shows that bits 127:32 of the result come from the first source rather than the accumulator and what that costs the masked intrinsics. VFCMADDCPH is the packed form, VFMULCSH covers the 32-bit scalar and the #UD when the destination is also a source, and VADDPH the format and the CPUID bits.

Exceptions and rounding#

Intel’s entry lists invalid, overflow, underflow, precision and denormal: they set their flags in MXCSR, but the instruction runs as if all were masked and so never faults on them. Its result is rounded to FP16 after each of the multiply-adds it is built from, so it can differ from a correctly rounded complex product and sum (Intel’s optimization manual, Sections 18.4.3 and 18.5.3). Register forms take {er}, which implies suppressing all exceptions (Section 18.5.5).

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 emit VFCMADDCSH for _mm_fcmadd_sch(a, b, c), into c’s register, followed by a move of the result to XMM0 since the destination may be neither a nor b. A scalar acc += x * ~y on _Complex _Float16 values, ~ being the conjugate in both compilers, is computed with real multiplies, additions and FMAs instead, with -ffast-math as without it.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFCMADDCSH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if xmm1.number == xmm2.number:
    fault(UD)
if not src3.is_memory:
    if xmm1.number == src3.number:
        fault(UD)
if k1[0]:
    ar = xmm2.f16[0]
    ai = xmm2.f16[1]
    br = src3.f16[0]
    bi = src3.f16[1]
    x = xmm1.f16[0]
    y = xmm1.f16[1]
    x = fmadd(ar, br, x)
    y = fmadd(ai, br, y)
    x = fmadd(ai, bi, x)
    y = fnmadd(ar, bi, y)
    xmm1.d[0] = y << 16 | x
elif zeroing:
    xmm1.d[0] = 0
# else: xmm1.d[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# x + y*i += (ar + ai*i)(br - bi*i)
# {er}: the form's rounding, not MXCSR.RC, and no flags
# exceptions as if masked (flags, never #XM): the SDM's claim, unchecked here
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E10

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFCMADDCSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VDBPSADBW
• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH

All 686 AVX10.1 instructions