VFCMULCPH

VFCMULCPH multiplies each complex number of its first source by the complex conjugate of the matching one in the second: for a + bi and c + di it computes ac + bd as the real part and bc - ad as the imaginary part, 16 products per zmm register. Intel’s optimization manual calls such a product a common operation, and finds the conjugation inside the multiply faster than a separate one (Section 18.4.3). It is VFMULCPH with the F2 prefix instead of F3, opcode D6h in EVEX map 6, and that page covers the layout of the pairs, the masking and broadcast per pair, the #UD when the destination is a source, and the rounding after each internal step; VFCMADDCPH adds the product to the destination.

Which operand is conjugated#

Intel’s entry conjugates the second source, so _mm512_fcmul_pch(a, b) computes a times the conjugate of b. Intel’s optimization manual describes _mm_conj_pch, which flips the sign of each imaginary part, and says that the compiler merges such a conjugation with a following multiply (Section 18.4.3). In our builds at -O2 with -march=x86-64-v4 -mavx512fp16, Clang 23 does: both _mm512_fmul_pch(_mm512_conj_pch(a), b) and _mm512_fmul_pch(a, _mm512_conj_pch(b)) become one VFCMULCPH, with the sources swapped for the first. GCC 14 computes the conjugate with a VPXORD against a broadcast sign mask and then multiplies with VFMULCPH.

Loops over complex halves#

z[i] = x[i] * ~y[i] over _Complex _Float16 arrays, ~ being GCC’s and Clang’s conjugate operator, stays scalar in both compilers by default: they compute each part with scalar FP16 arithmetic and call the library’s __mulhc3 only for a NaN result. With -ffast-math or -fcx-limited-range, GCC vectorizes it to VFCMULCPH with y read from memory; Clang keeps to real multiplies, additions and FMAs on separated real and imaginary parts.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFCMULCPH.

In the optimization guide

What the optimization guide says about VFCMULCPH, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: VPERMD, VPERMQ, VPERMPS, VPERMPD, VPMULLQ, vrange, vgetmant and the half-precision complex multiplications wait for the old value of their destination, which they then overwrite.
• Vectors, AVX-512 and AMX: AVX-512 FP16 adds and multiplies 32 half-precision values per 512-bit register with a latency of four cycles; division and square root take about 31. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if zmm1.number == zmm2.number:
    fault(UD)
if not src3.is_memory:
    if zmm1.number == src3.number:
        fault(UD)
for i in range(VL // 32):
    if k1[i]:
        ar = zmm2.f16[2 * i]
        ai = zmm2.f16[2 * i + 1]
        br = src3.f16[2 * i]
        bi = src3.f16[2 * i + 1]
        x = mul(ar, br)
        y = mul(ai, br)
        x = fmadd(ai, bi, x)
        y = fnmadd(ar, bi, y)
        zmm1.d[i] = y << 16 | x
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# (ar + ai*i)(br - bi*i) = x + y*i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# exceptions as if masked (flags, never #XM): the SDM's claim, unchecked here
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFCMULCPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VDIVPD
• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS

All 686 AVX10.1 instructions