VFCMULCSH

VFCMULCSH multiplies the lowest complex number of its first source by the complex conjugate of the lowest one in the second: for x = a + bi and y = c + di it writes ac + bd to bits 15:0 and bc - ad to bits 31:16 of the destination. Bits 127:32 come from the first source and the bits above 127 are cleared. It is the scalar form of VFCMULCPH, whose page explains which operand is conjugated and how compilers merge a separate conjugation; VFMULCSH covers the 32-bit scalar, the per-pair mask bit and the #UD when the destination is a source, and VFMULCPH the rounding after each internal step.

Encoding and use#

The opcode is D7h with the F2 prefix in EVEX map 6, where VFMULCSH has F3; the memory operand is one 32-bit pair, and register forms take {er}. Intel’s entry lists invalid, overflow, underflow, precision and denormal, which set their MXCSR flags while the instruction runs as if all were masked.

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 emit VFCMULCSH for _mm_fcmul_sch(a, b) and _mm_cmul_sch(a, b), the product of a with the conjugate of b, writing a third register and moving the result back. C code does not reach it: a * ~b on _Complex _Float16 values, ~ being GCC’s and Clang’s conjugate, is computed with scalar arithmetic in both, with a call to __mulhc3 only for a NaN result, and with -ffast-math GCC flips the sign of the imaginary half with a VXORPS and multiplies with VMULSH and scalar FMAs, while Clang uses VMULPH and VFMSUBADD213PH.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFCMULCSH.

In the optimization guide

What the optimization guide says about VFCMULCSH, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: VPERMD, VPERMQ, VPERMPS, VPERMPD, VPMULLQ, vrange, vgetmant and the half-precision complex multiplications wait for the old value of their destination, which they then overwrite.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if xmm1.number == xmm2.number:
    fault(UD)
if not src3.is_memory:
    if xmm1.number == src3.number:
        fault(UD)
if k1[0]:
    ar = xmm2.f16[0]
    ai = xmm2.f16[1]
    br = src3.f16[0]
    bi = src3.f16[1]
    x = mul(ar, br)
    y = mul(ai, br)
    x = fmadd(ai, bi, x)
    y = fnmadd(ar, bi, y)
    xmm1.d[0] = y << 16 | x
elif zeroing:
    xmm1.d[0] = 0
# else: xmm1.d[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# (ar + ai*i)(br - bi*i) = x + y*i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# exceptions as if masked (flags, never #XM): the SDM's claim, unchecked here
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E10

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFCMULCSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VDIVPH
• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD

All 686 AVX10.1 instructions