VFIXUPIMMPD

VFIXUPIMMPD patches the special cases of a vector math routine on doubles. It sorts each double of its first source into one of eight classes, QNaN, SNaN, zero, +1.0, -infinity, +infinity, other negative and other positive, and replaces the destination element with the result that a 4-bit code names for that class. The codes come from the low doubleword of the matching quadword of the second source, eight codes in one table, and the immediate says which classes raise ZE or IE. VFIXUPIMMPS has the table of classes, codes and immediate bits; the double form uses the same, with its constants as doubles. VFIXUPIMMSD is the scalar form.

Recorded on Zen 5#

• By class. With the tables 87654321h and 76543210h, 1.0 gave -infinity (code 4), -2.0 an infinity of its sign (code 6), 2.0 -0 (code 7), and a negative denormal under DAZ counted as zero and gave the default NaN, FFF8000000000000h (code 3).
• SNaN without IE. An SNaN with the immediate 40h came back quieted (code 2), and MXCSR stayed clean: only immediate bit 4 makes an SNaN signal.
• Signalling. With the immediate AAh and IE masked, +infinity became +0 (code 8) and set IE.
• Denormals as zeros. Under DAZ, denormal inputs with the tables 0FEDCBA9h and FEDCBA98h gave 0.5 and 1.0, the zero codes Bh and Ah.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 emit VFIXUPIMMPD only for the intrinsics: _mm512_fixupimm_pd(r, x, t, imm) takes the result to patch, the inputs and the tables, and a constant table becomes a broadcast, a VPBROADCASTQ from a register in GCC and a {1to8} memory operand in Clang. Neither uses it for C’s division or library calls.

AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP0 or FP1 and 2 cycles at every width.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = zmm1.f64[i]
        b = zmm2.f64[i]
        sc = src3.sq[i]
        x = fixupimm(a, b, sc, imm8)
        zmm1.f64[i] = x
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# sc: four bits for each class of b that name the result; imm8: the classes that raise ZE or IE
# m64bcst: src3.f64[i] is the m64 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFIXUPIMMPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VDIVPS
• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH

All 686 AVX10.1 instructions