VFIXUPIMMPS

VFIXUPIMMPS patches the special cases of a vector math routine without branches. It sorts each single of its first source into one of eight classes and replaces the destination element with a value that a table names for that class; the table is the matching doubleword of the second source, eight 4-bit codes, one per class. Code 0 keeps the destination, so a routine computes its ordinary result first and then lets VFIXUPIMMPS overwrite the elements whose input was special.

Classes and codes#

The classes, in the order of their codes in the table (bits 3:0 for the first, 31:28 for the last), are QNaN, SNaN, zero, +1.0, -infinity, +infinity, any other negative number and any other positive number. The codes name these results:

A denormal input counts as a zero under MXCSR.DAZ and as a number otherwise. Zen 5 recorded the constants as 42B40000h for 90.0 and 3FC90FDBh for pi/2, the single nearest to it. The table is usually one constant for every element: _mm512_fixupimm_ps(result, x, _mm512_set1_epi32(table), imm8).

For a reciprocal, for example, the table 00870622h makes a NaN input quiet, a zero an infinity of its sign, -infinity -0 and +infinity +0, and keeps the computed value for every other class; the immediate 11h adds the flags C expects, ZE for a zero and IE for an SNaN.

The exceptions it raises#

The immediate does not choose results; it says which classes signal an exception: a zero can raise ZE (bit 0) or IE (bit 1), +1.0 ZE or IE (bits 2 and 3), and an SNaN, -infinity, a negative number and +infinity IE (bits 4 to 7). Where the exception is unmasked in MXCSR, the instruction faults with #XM, as Zen 5 recorded; the zmm register form takes {sae} to report nothing.

AMD’s Zen 5 guide lists VFIXUPIMMPS as one macro-op with a latency of 2 cycles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = zmm1.f32[i]
        b = zmm2.f32[i]
        sc = src3.sd[i]
        x = fixupimm(a, b, sc, imm8)
        zmm1.f32[i] = x
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# sc: four bits for each class of b that name the result; imm8: the classes that raise ZE or IE
# m32bcst: src3.f32[i] is the m32 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFIXUPIMMPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VDIVSD
• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMSD
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS

All 686 AVX10.1 instructions