VFIXUPIMMSD

VFIXUPIMMSD is the scalar form of VFIXUPIMMPD: it sorts the low double of its first source into one of eight classes and replaces the low double of the destination with the result that the class’s 4-bit code, taken from the low doubleword of the second source, names, while bits 127:64 come from the first source. Code 0 keeps the destination, so the instruction patches a result already computed, and the immediate chooses which classes raise ZE or IE. VFIXUPIMMPS has the table of classes, codes and immediate bits. VFIXUPIMMSS is the single-precision form. The EVEX encoding adds a write mask on the one element and {sae}.

Recorded on Zen 5#

• Denormal as zero. With DAZ set, the denormal 00000000FEDCBA98h, used as both input and table, counted as zero, whose code Ah gave 1.0; bits 127:64 came from the same register.
• Code 0 under zeroing. With bit 0 of the mask set and {z}, -2.0, an ordinary negative number whose code was 0, left the destination’s 192.0 in place.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile _mm_fixupimm_sd(r, x, t, imm) to vfixupimmsd xmm0, xmm1, xmm2, imm with r in XMM0, and nothing else in C produces it.

AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP0 or FP1 and 2 cycles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm1.f64[0]
    b = xmm2.f64[0]
    sc = src3.sq[0]
    xmm1.f64[0] = fixupimm(a, b, sc, imm8)
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# {sae}: no exception flags
# sc: four bits for each class of b that name the result; imm8: the classes that raise ZE or IE
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFIXUPIMMSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VDIVSH
• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSS
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS
• VFMADDCPH

All 686 AVX10.1 instructions