VFIXUPIMMSS

VFIXUPIMMSS is the scalar form of VFIXUPIMMPS, whose page has the classes, the codes and the immediate bits: it sorts the low single of its first source into one of eight classes, replaces the low single of the destination with the value that the class’s 4-bit code in the low doubleword of the second source names, and takes bits 127:32 from the first source. Code 0 keeps the destination, so a routine computes its result first and patches only the special inputs. VFIXUPIMMSD is the double-precision form. It came with AVX512F, with a write mask on the one element and {sae}.

Recorded on Zen 5#

• A large number. 543210FEh, an ordinary positive single, used as input and table, took code 5 and became +infinity, 7F800000h.
• An SNaN. FF800001h with the table EDCBA987h took code 8 and gave +0; the immediate 55h, whose bit 4 makes an SNaN signal, set IE.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile _mm_fixupimm_ss to VFIXUPIMMSS; a constant mask with bit 0 set, as in _mm_maskz_fixupimm_ss(3, ...), is dropped.

AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP0 or FP1 and 2 cycles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm1.f32[0]
    b = xmm2.f32[0]
    sc = src3.sd[0]
    xmm1.f32[0] = fixupimm(a, b, sc, imm8)
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {sae}: no exception flags
# sc: four bits for each class of b that name the result; imm8: the classes that raise ZE or IE
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFIXUPIMMSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VDIVSS
• VDPBF16PS
• VEXPANDPD
• VEXPANDPS
• VEXTRACTF32X4
• VEXTRACTF32X8
• VEXTRACTF64X2
• VEXTRACTF64X4
• VEXTRACTI32X4
• VEXTRACTI32X8
• VEXTRACTI64X2
• VEXTRACTI64X4
• VEXTRACTPS
• VFCMADDCPH
• VFCMADDCSH
• VFCMULCPH
• VFCMULCSH
• VFIXUPIMMPD
• VFIXUPIMMPS
• VFIXUPIMMSD
• VFMADD132PD
• VFMADD132PH
• VFMADD132PS
• VFMADD132SD
• VFMADD132SH
• VFMADD132SS
• VFMADD213PD
• VFMADD213PH
• VFMADD213PS
• VFMADD213SD
• VFMADD213SH
• VFMADD213SS
• VFMADD231PD
• VFMADD231PH
• VFMADD231PS
• VFMADD231SD
• VFMADD231SH
• VFMADD231SS
• VFMADDCPH
• VFMADDCSH

All 686 AVX10.1 instructions